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this document contains information on one or more products under development at spansion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this pr oposed product without notice. publication number s71ws-n-02 revision a amendment 2 issue date april 11, 2005 s71ws512nx0/s71ws256nx0 based mcps stacked multi-chip product (mcp) 256/512 megabit (32m/1 6m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory with 128/64megabit (8m/4m x 16-bit) cosmoram data sheet advance information notice to readers: this document states the curre nt technical specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notice on data sheet designations spansion llc issues data sheets with advance information or preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, includ- ing development, qualification, initial production , and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de- sign. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe- cific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the prod- uct may discontinue. spansion llc therefore pl aces the following conditions upon advance information content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the pr oduct development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initia l production, and the subsequent phases in the manufacturing process that occur before full prod uction is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as- pects of production under consideration. span sion places the following conditions upon preliminary content: ?this document states the current technical specific ations regarding the spansion product(s) described herein. the preliminary status of this document indi cates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of products with different designations (advance in- formation, preliminary, or full production). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc characteristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to th e notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designat ion is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option , temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incor- rect specification. spansion llc applies the follo wing conditions to documents in this category: ?this document states the current technical specific ations regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
publication number s71ws-n-02 revision a amendment 2 issue date april 11, 2005 general description the s71ws-n series is a product line of stacked multi-chip product (mcp) packages and consists of the following items: ? one or more flash memory die ? cosmoram-compatible psram the products covered by this document are listed in the table below. for details about their spec- ifications, please refer to the individual constituent datasheet for further details. distinctive characteristics mcp features ? power supply voltage of 1.7 v to 1.95 v ? burst speed: 54 mhz, 66 mhz ? package ? 8 x 11.6 mm, 9 x 12 mm ? operating temperature ? wireless, ?25c to +85c s71ws512nx0/s71ws256nx0 based mcps stacked multi-chip product (mcp) 256/512 megabit (32m/1 6m x 16 bit) cmos 1.8 volt-only simultaneous read/write, burst-mode flash memory with 128/64megabit (8m/4m x 16-bit) cosmoram advance information device flash density psram density 512 mb 256 mb 128 mb 64 mb 128 mb 64 mb 32 mb 16 mb s71ws512nd0 ?? s71ws512nc0 ?? s71ws256nd0 ?? s71ws256nc0 ??
4 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information contents s71ws512nx0/s71ws256nx0 base d mcps . . . . . . . . . . . . . . . . . . . . . . . . 3 1 product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 connection diagrams/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 special handling instructions for fbga packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 cosmoram based pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 look-ahead connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.1 tla084?84-ball fine-pitch ball grid array (fbga) 11.6 x 8.0 x 1.2 mm. . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.2 tsd084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . .18 s29ws-n mirrorbit? flash family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 synchronous (burst) read mode and configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3.1 continuous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3.2 8-, 16-, 32-word linear burst read with wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3.3 8-, 16-, 32-word linear burst without wrap around . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.5.1 single word programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.5.2 write buffer programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.5.4 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.5.5 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.5.6 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.5.7 accelerated program/chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.5.8 unlock bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.5.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.6 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.7 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.8 handshaking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.9 hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.10 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.4 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.7 hardware data protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.7.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.7.2 acc method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.7.3 low v cc write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 5 advance information 9.7.4 write pulse glitch protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.7.5 power-up write inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 10.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.2 customer secured silicon sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.3 secured silicon sector entry and secured silicon sector exit command sequences. . . . . . . . . . . . . . . . . . . . . 64 12 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.6 v cc power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.7 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.8.1 clk characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.8.2 synchronous/burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.8.3 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.8.4 ac characteristics?asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.8.5 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.8.6 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.8.7 erase and programming performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.8.8 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14 commonly used terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 cosmoram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 15 pin description (32m) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16 cosmoram functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 16.1 asynchronous operation (page mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 16.2 synchronous operation (burst mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17 state diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 17.1 initial/standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 17.2 asynchronous operation state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 17.3 synchronous operation state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 18.1 power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 18.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 18.3 cr set sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 18.4 address key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.5 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.6 burst read/write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 18.7 clk input function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 18.8 adv# input function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 18.9 wait# output function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 18.10 latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 18.11 address latch by adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 18.12 burst length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 18.13 single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 18.14 write control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
6 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 18.15 burst read suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 18.16 burst write suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 18.17 burst read termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 18.18 burst write termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 19 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 20 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 21 package pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 22 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 23 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 23.1 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 23.2 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 23.3 synchronous operation - clock input (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 23.4 synchronous operation - address latch (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 23.5 synchronous read operation (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 23.6 synchronous write operation (burst mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 23.7 power down parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 23.8 other timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 23.9 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 23.10 ac measurement output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 24 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 25 revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 7 advance information ta b l e s table 2.1 mcp configurations and valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3.1 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7.1 s29ws256n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7.2 s29ws128n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7.3 s29ws064n sector & memory address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8.1 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8.2 address latency (s29ws256n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8.3 address latency (s29ws128n/s29ws064n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8.4 address/boundary crossing latency (s29ws256n @ 80/66 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 8.5 address/boundary crossing latency (s29ws256n @ 54mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8.6 address/boundary crossing latenc y (s29ws128n/s29ws064n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 8.7 burst address groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8.8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8.9 autoselect addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8.10 autoselect entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8.11 autoselect exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8.12 single word program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 8.13 write buffer program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8.14 sector erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 8.15 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8.16 erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8.17 erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8.18 program suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 8.19 program resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 8.20 unlock bypass entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 8.21 unlock bypass program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 8.22 unlock bypass reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 8.23 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 8.24 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 9.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 9.2 sector protection schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 11.1 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 11.2 secured silicon sector entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 11.3 secured silicon sector program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 11.4 secured silicon sector exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 12.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 13.1 memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 13.2 sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 13.3 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 13.4 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 13.5 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 13.6 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information figures figure 8.1 synchronous/asynchronous state diagram ................ ............................................................... ............25 figure 8.2 synchronous read ..................................................................................................... .......................28 figure 8.3 single word program.................................................................................................. .......................34 figure 8.4 write buffer programming operation ................................................................................... ................38 figure 8.5 sector erase operation ............................................................................................... .......................40 figure 8.6 write operation status flowch art ..................................................................................... ...................47 figure 9.1 advanced sector protection/unp rotection .............................................................................. ...............53 figure 9.2 ppb program/erase algorithm .......................................................................................... ...................56 figure 9.3 lock register program algorith m...................................................................................... ...................59 figure 12.1 maximum negative overshoot wave form ................................................................................. ............66 figure 12.2 maximum positive overshoot waveform ................. ................................................................ ..............66 figure 12.3 test setup .......................................................................................................... .............................67 figure 12.4 input waveforms and measuremen t levels .............................................................................. .............67 figure 12.5 v cc power-up diagram .............................................................................................................. ........68 figure 12.6 clk characterization ................................................................................................ .........................70 figure 12.7 clk synchronous burst mode read..................................................................................... .................71 figure 12.8 8-word linear burst with wrap around................................................................................ .................72 figure 12.9 8-word linear burst without wrap around ............. ................................................................ ...............72 figure 12.10 linear burst with rdy set one cycle before data .. .................................................................. ..............73 figure 12.11 asynchronous mode read............................................................................................. ......................74 figure 12.12 reset timings...................................................................................................... .............................74 figure 12.13 chip/sector erase operation timings ................................................................................ ...................76 figure 12.14 asynchronous program operation timings ............................................................................. ...............77 figure 12.15 synchronous program operation timings .............................................................................. ...............78 figure 12.16 accelerated unlock bypass prog ramming timing ....................................................................... ............78 figure 12.17 data# polling timings (during embedded algorithm) .. ................................................................ ...........79 figure 12.18 toggle bit timings (during embedded algorithm) .... ................................................................. .............79 figure 12.19 synchronous data polling timings/toggle bit timings ................................................................ ............80 figure 12.20 dq2 vs. dq6 ........................................................................................................ ............................80 figure 12.21 latency with boundary crossing when frequency > 66 mhz............................................................. .......81 figure 12.22 latency with boundary crossing into program/erase bank ............................................................. .........82 figure 12.23 example of wait state inse rtion .................................................................................... ......................83 figure 12.24 back-to-back read/write cycl e timings .............................................................................. .................84 figure 17.1 initial standby state diagra m ....................................................................................... .................... 100 figure 17.2 asynchronous operation state diagram ................................................................................ ............. 100 figure 17.3 synchronous operation diagram ....................................................................................... ................ 101 figure 18.1 burst read operation ................................................................................................ ...................... 104 figure 18.2 burst write operat ion ............................................................................................... ....................... 105 figure 18.3 read latency diagram ................................................................................................ ..................... 107 figure 18.4 write controls ...................................................................................................... .......................... 109 figure 18.5 burst read suspend diagram .......................................................................................... ................. 110 figure 18.6 burst write suspend diagram ......................................................................................... .................. 110 figure 18.7 burst read termination diagram...................................................................................... ................. 111 figure 18.8 burst write terminat ion diagram ..................................................................................... ................. 111 figure 23.1 output load circuit ................................................................................................. ........................ 120 figure 24.1 asynchronous read timing #1-1 (basic timing) ........................................................................ .......... 121 figure 24.2 asynchronous read timing #1-2 (basic timing) ........................................................................ .......... 121 figure 24.3 asynchronous read timing #2 (oe# & address access) . ................................................................. ..... 122 figure 24.4 asynchronous read timing #3 (lb# / ub# byte acce ss) ................................................................. ..... 122 figure 24.5 asynchronous read timing #4 (page address access af ter ce1# control access) .................................... 123 figure 24.6 asynchronous read timing #5 (random and page addr ess access) ....................................................... 1 23 figure 24.7 asynchronous write timing #1-1 (basic timing) ....................................................................... .......... 124 figure 24.8 asynchronous write timing #1-2 (basic timing) ....................................................................... .......... 124 figure 24.9 asynchronous write timing #2 (we# control) ........ .................................................................. .......... 125
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 9 advance information figure 24.10 asynchronous write timing #3-1 (we# / lb# / ub# by te write control) ............................................... 1 25 figure 24.11 asynchronous write timing #3-2 (we# / lb# / ub# by te write control) ............................................... 1 26 figure 24.12 asynchronous write timing #3-3 (we# / lb# / ub# by te write control) ............................................... 1 26 figure 24.13 asynchronous write timing #3-4 (we# / lb# / ub# by te write control) ............................................... 1 27 figure 24.14 asynchronous read / write tim ing #1-1 (ce1# control) ............................................................... ....... 127 figure 24.15 asynchronous read / write timin g #1-2 (ce1# / we# / oe# control) ................................................... 128 figure 24.16 asynchronous read / write timing #2 (oe#, we# cont rol) ............................................................. ..... 128 figure 24.17 asynchronous read / write timing #3 (oe,# we#, lb #, ub# control) .................................................. 1 29 figure 24.18 clock input timing ................................................................................................. ......................... 129 figure 24.19 address latch timing (synchronous mode) ............................................................................ ............. 130 figure 24.20 32m synchronous read timing #1 (oe# control) ....................................................................... ......... 131 figure 24.21 32m synchronous read timing #2 (ce1# control) ...................................................................... ........ 132 figure 24.22 32m synchronous read timing #3 (adv# control) ...................................................................... ........ 133 figure 24.23 synchronous read - wait# outp ut timing (continuous read) ........................................................... ... 134 figure 24.24 64m synchronous read timing #1 (oe# control) ....................................................................... ......... 135 figure 24.25 64m synchronous read timing #2 (ce1# control) ...................................................................... ........ 136 figure 24.26 64m synchronous read timing #3 (adv# control) ...................................................................... ........ 137 figure 24.27 synchronous write timing #1 (w e# level control) .................................................................... ......... 138 figure 24.28 synchronous write timing #2 (we# single clock pulse control)....................................................... ..... 139 figure 24.29 synchronous write timing #3 (a dv# control) ......................................................................... ........... 140 figure 24.30 synchronous write timing #4 (we# level control, single write)...................................................... ..... 141 figure 24.31 32m synchronous read to write timing #1(ce1# control) .............................................................. ..... 142 figure 24.32 32m synchronous read to write timing #2(adv# contro l) .............................................................. ..... 143 figure 24.33 64m synchronous read to write timing #1(ce1# control) .............................................................. ..... 144 figure 24.34 64m synchronous read to write timing #2(adv# contro l) .............................................................. ..... 145 figure 24.35 synchronous write to read timing #1 (ce1# control) ................................................................. ........ 146 figure 24.36 synchronous write to read timing #2 (adv# control)................................................................. ........ 147 figure 24.37 power-up timing #1 ................................................................................................. ....................... 148 figure 24.38 power-up timing #2 ................................................................................................ ....................... 148 figure 24.39 power down entry and exit timing ................................................................................... ................. 148 figure 24.40 standby entry timing after read or write........................................................................... ................ 149 figure 24.41 configuration regist er set timing #1 (a synchronous operation) ...................................................... ..... 149 figure 24.42 configuration regist er set timing #2 (synch ronous operation)....................................................... ...... 150
10 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 1 product selector guide note: 0 (protected), 1 (unprotected [default state]) device model numbers flash psram density (mb) flash speed (mhz) psram speed (mhz) dyb power-up state ( see note ) psram supplier package (mm) s71ws256nc0 au ws256n 64 54 54 0 cosmoram 1 11.6x8.0x1.2 az 1 at 66 66 0 ay 1 s71ws256nd0 yu 128 54 54 0 9x12x1.2 yz 1 yt 66 66 0 yy 1 s71ws512nc0 au ws512n 64 54 54 0 11.6x8.0x1.2 az 1 at 66 66 0 ay 1
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 11 advance information 2 ordering information the ordering part number is formed by a valid combination of the following: package marking note: the package marking omits the leading s from the ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s71ws 256 n c 0 ba w a k 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel ram supplier, dyb power up, speed combinations u = 1 = cosmoram 1, 0, 54 mhz z = 1 = cosmoram 1, 1, 54 mhz t = 1 = cosmoram 1, 0, 66 mhz y = 1 = cosmoram 1, 1, 66 mhz package modifier a = 1.2 mm, 8 x 11.6, 84-ball fbga y = 1.2 mm, 9 x 12, 84-ball fbga temperature range w = wireless (-25 c to +85 c) package type ba = very thin fine-pitch bga lead (pb)-free compliant package bf = very thin fine-pitch bga lead (pb)-free package chip contents?2 no content psram density c = 64mb d = 128mb process technology n = 110nm mirrorbit? technology flash density 512 = 512mb (2x256mb) 256 = 256mb device family s71ws= multi-chip product 1.8 volt-only simultaneous read/write burst mode flash memory + xram table 2.1 mcp configurations and valid combinations valid combinations s71ws256n c 0ba, bf w a u, z, t, y dy s71ws512n c a
12 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 3 input/output descriptions table 3.1 identifies the input and output package connections provided on the device. table 3.1 input/output descriptions symbol description a23-a0 address inputs dq15-dq0 data input/output oe# output enable input. asynchronous relative to clk for the burst mode. we# write enable input. v ss ground nc no connect; not connected internally rdy ready output. indicates the status of the burst read. the wait# pin of the psram is tied to rdy. clk clock input. in burst mode, after th e initial word is outp ut, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in as ynchronous mode avd# address valid input. indicates to device that th e valid address is present on the address inputs. low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. high = device ignores address inputs f-rst# hardware reset input. low = device resets and returns to reading array data f-wp# hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. f-acc accelerated input. at v hh , accelerates programming; automatica lly places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. r-ce1# chip-enable input for psram. r-ce2 chip-enable 2 for cosmoram only. f1-ce# chip-enable input for flash 1. asynchronous relative to clk for burst mode. f2-ce# chip-enable input for flash 2. asynchronous relative to clk for burst mode. this applies to the 512mb mcp only. f-vcc flash 1.8 volt-only single power supply. r-vcc psram power supply. r-ub# upper byte control (psram). r-lb# lower byte control (psram) dnu do not use
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 13 advance information 4 mcp block diagram notes: 1. r-cr2 is only present in cosmoram-compatible psram. 2. for 1 flash + psram, f1-ce# = ce#. for 2 flash + psram, ce# = f1-ce# and f2-ce# is the chip-enable pin for the second flash. 3. only needed for s71ws512n. 4. for the 128m psram devices, there are 23 shared addresses. v id v cc rdy psram flash 1 dq15 to dq0 flash-only address shared address f1-ce# acc r-ub# r-ce2 r-vcc v cc v ccq f-vcc 22 clk clk wp# oe# we# f-rst# avd# ce# acc wp# oe# we# reset# avd# rdy v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 r-ce1# ce# we# oe# ub# r-lb# lb# 22 f2-ce# clk avd# flash 2 wait# ce2 ( note 4 ) ( note 1 ) ( note 3 ) ( note 3 )
14 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 5 connection diagrams/physical dimensions this section contains the i/o designations and package specifications for the s71ws-n. 5.1 special handling instruc tions for fbga packages special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be da maged if exposed to ultrasonic cleaning meth- ods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 15 advance information 5.2 connection diagrams 5.2.1 cosmoram based pinout notes: 1. in mcps based on a single s29ws256n (s71ws256n), ball b5 is rfu. in mcps based on two s29ws256n (s71ws512), ball b5 is f2-ce#. 2. addresses are shared between flash and ram depending on the density of the psram. mcp flash-only addresses shared addresses mcp flash-only addresses shared addresses s71ws256nc0 a23 ? a22 a21 ? a0 s71ws512nc0 a23 ? a22 a21-a0 s71ws256nd0 a23 a22 ? a0 s71ws512nd0 a23 a22-a0 a7 a3 a2 dq8 dq14 r-ce1# r-lb# acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 r-ub# f-rst# r-ce2 a19 a12 a15 d2 d3 d4 d5 d7 d8 d9 a5 a18 rdy a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 f1-ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu h2 h3 h4 h5 h6 h7 h8 h9 dq10 f-vcc r-vcc dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu clk f2-ce# rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu f-vcc rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 avd# rfu rfu rfu rfu f-wp# rfu rfu a1 a10 m1 m10 dnu dnu dnu dnu 1st ram only shared 1st flash only legend d6 2nd flash only 84-ball fine-pitch ball grid array cosmoram-based pinout (top view, balls facing down)
16 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 5.2.2 look-ahead connection diagram notes: ball 3.0 v v cc 1.8 v v cc 1. in a 3.0v system, the gl device used as data has to have wp tied to v cc 2. f1 and f2 denote xip/flash, f3 and f4 denote data/companion flash d2 nc f-wp# d5 wp#/acc acc f5 ry/by f-rdy/r-wait# legend: xram shared psram only flash/xram shared flash/data shared rfu (reserved for future use) code flash only x mirrorbit data only x x x x x x x x x x x x x x rfu b1 b10 rfu b2 rfu b9 rfu f-dqs0 n1 n1 f-dqs1 n10 rfu n2 rfu n9 rfu p1 rfu p10 p2 rfu rfu p9 a1 rfu rfu a10 rfu a2 rfu a9 d3 a7 acc d5 r-lb# d4 d7 a8 wp# d2 d8 a11 f3-ce# d9 d6 we# f3 f3 a5 f5 rdy/wait# f4 f4 a18 f7 f7 a9 f2 f2 a2 f8 f8 a13 f9 f9 a21 f6 f6 a20 j3 oe# j5 dq3 j4 dq9 j7 dq13 f1-ce# j2 j8 dq15 r-cre or r-mrs j9 j6 dq4 l3 l3 dq8 l5 l5 dq11 l4 l4 dq2 l7 l7 dq5 r-vcc l2 l8 l8 dq14 wp# l9 l6 l6 a25 c3 vss f2-ce# c5 c4 clk f-clk# c7 avd# c2 r-oe# c8 f2-oe# c9 f-vcc c6 c6 c 6 c 6 e3 a6 f-rst# c7 r-ub# d4 e7 a19 e2 a3 e8 a12 e9 a15 r1-ce2 e6 a4 g3 g3 r2-ce1 g5 a17 g4 g4 a10 g7 g7 a1 g2 g2 a14 g8 g8 a22 g9 g9 a23 g6 g6 h3 h3 vss r2-vcc h5 h4 h4 dq1 h7 dq6 h2 h2 a0 h8 a24 h9 a16 r2-ce2 h6 dq0 k3 k3 f-vcc k5 dq10 k4 k4 k7 k7 dq12 r1-ce1# k2 dq7 k8 k8 k9 k9 vss r1-vcc e6 m3 a26 f-vcc m5 m4 vss r-vccq m7 m2 a27 f-vccq m8 r-clk# m9 f4-ce# m6
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 17 advance information 5.3 physical dimensions 5.3.1 tla084?84-ball fine-pitch ball grid array (fbga) 11.6 x 8.0 x 1.2 mm note: bsc is an ansi standard for basic space centering 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
18 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 5.3.2 tsd084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.2 mm 3426\ 16-038.2 2 package tsd 084 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.94 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 m c mc ab 0.08 pin a1 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd
publication number s71ws-n-02 revision a amendment 2 issue date april 11, 2005 general description the spansion s29ws256/128/064n are mirrorbit? flash products fabricated on 110 nm process technology. these burst mode flash devices are capable of perform ing simultaneous read and write operatio ns with zero latency on two separate banks using separate data and address pins. these pr oducts can operate up to 80 mhz and use a single v cc of 1.7 v to 1.95 v that makes them ideal for today?s demanding wireless applications requiring higher density, better per- formance and lowered power consumption. distinctive characteristics ? single 1.8 v read/program/erase (1.70?1.95 v) ? 110 nm mirrorbit? technology ? simultaneous read/write operation with zero latency ? 32-word write buffer ? sixteen-bank architecture consisting of 16/8/4 mwords for ws256n/128n/064n, respectively ? four 16 kword sectors at both top and bottom of memory array ? 254/126/62 64 kword sectors (ws256n/128n/ 064n) ? programmable burst read modes ? linear for 32, 16 or 8 words linear read with or without wrap-around ? continuous sequential read mode ? secured silicon sector region consisting of 128 words each for factory and customer ? 20-year data retention (typical) ? cycling endurance: 100,000 cycles per sector (typical) ? rdy output indicates data available to system ? command set compatible with jedec (42.4) standard ? hardware (wp#) protection of top and bottom sectors ? dual boot sector config uration (top and bottom) ? offered packages ? ws064n: 80-ball fbga (7 mm x 9 mm) ? ws256n/128n: 84-ball fbga (8 mm x 11.6 mm) ? low v cc write inhibit ? persistent and password methods of advanced sector protection ? write operation status bits indicate program and erase operation completion ? suspend and resume commands for program and erase operations ? unlock bypass program command to reduce programming time ? synchronous or asynchronous program operation, independent of burst control register settings ? acc input pin to reduce factory programming time ? support for common fl ash interface (cfi) ? industrial temperature range (contact factory) performance characteristics s29ws-n mirrorbit? flash family s29ws256n, s29ws128n, s29ws064n 256/128/64 megabit (16/8/4 m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burst mode flash memory data sheet advance information read access times speed option (mhz) 80 66 54 max. synch. latency, ns (t iacc ) 80 80 80 max. synch. burst access, ns (t bacc ) 9 11.2 13.5 max. asynch. access time, ns (t acc ) 80 80 80 max ce# access time, ns (t ce ) 80 80 80 max oe# access time, ns (t oe ) 13.5 13.5 13.5 current consumption (typical values) continuous burst read @ 66 mhz 35 ma simultaneous operation (asynchronous) 50 ma program (asynchronous) 19 ma erase (asynchronous) 19 ma standby mode (asynchronous) 20 a typical program & erase times single word programming 40 s effective write buffer programming (v cc ) per word 9.4 s effective write buffer programming (v acc ) per word 6 s sector erase (16 kword sector) 150 ms sector erase (64 kword sector) 600 ms
20 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 6 additional resources visit www.amd.com and www.fujitsu.com to obtain the following related documents: application notes ? using the operation status bits in amd devices ? understanding burst mode flash memory devices ? simultaneous read/write vs. erase suspend/resume ? mirrorbit? flash memory write buffer programming and page buffer read ? design-in scalable wireless solutions with spansion products ? common flash interface version 1.4 vendor specific extensions specification bulletins contact your local sales office for details. drivers and software support ? spansion low-level drivers ? enhanced flash drivers ? flash file system cad modeling support ? vhdl and verilog ? ibis ? orcad technical support contact your local sales office or contact spansion llc directly for additional technical support: email us and canada: hw.support@amd.com asia pacific: asia.support@amd.com europe, middle east, and africa japan: http://edevice.fujitsu.com/jp/support/tech/#b7 frequently asked questions (faq) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 phone us: (408) 749-5703 japan (03) 5322-3324 spansion llc locations 915 deguigne drive, p.o. box 3453 sunnyvale, ca 94088-3453, usa telephone: 408-962-2500 or 1-866-spansion spansion japan limited 4-33-4 nishi shinjuku, shinjuku-ku tokyo, 160-0023 telephone: +81-3-5302-2200 facsimile: +81-3-5302-2674 http://www.spansion.com
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 21 advance information 7 product overview the s29ws-n family consists of 256, 128 and 64mbit, 1.8 volts-only, simultaneous read/write burst mode flash device optimized for today?s wireless designs that demand a large storage array, rich functionality, and low power consumption. these devices are organized in 16, 8 or 4 mwords of 16 bits each and ar e capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. these products also offer single word programming or a 32-word buffer for programming with program/erase and suspend function ality. additional features include: ? advanced sector protection methods for protecting sectors as required ? 256 words of secured silicon area for storing customer and factory secured information. the secured silicon sector is one time programmable. 7.1 memory map the s29ws256/128/064n mbit devices consist of 16 banks organized as shown in tables table 7.1 , ta b l e 7 . 2 , and ta b l e 7 . 3 . note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not exp licitly listed (such as sa005?sa017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 7.1 s29ws256n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 2 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 15 128 sa004 to sa018 010000h?01ffffh to 0f0000h?0fffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) 2 mb 16 128 1 sa019 to sa034 100000h?10ffffh to 1f0000h?1fffffh 2 mb 16 128 2 sa035 to sa050 200000h?20ffffh to 2f0000h?2fffffh 2 mb 16 128 3 sa051 to sa066 300000h?30ffffh to 3f0000h?3fffffh 2 mb 16 128 4 sa067 to sa082 400000h?40ffffh to 4f0000h?4fffffh 2 mb 16 128 5 sa083 to sa098 500000h?50ffffh to 5f0000h?5fffffh 2 mb 16 128 6 sa099 to sa114 600000h?60ffffh to 6f0000h?6fffffh 2 mb 16 128 7 sa115 to sa130 700000h?70ffffh to 7f0000h?7fffffh 2 mb 16 128 8 sa131 to sa146 800000h?80ffffh to 8f0000h?8fffffh 2 mb 16 128 9 sa147 to sa162 900000h?90ffffh to 9f0000h?9fffffh 2 mb 16 128 10 sa163 to sa178 a00000h?a0ffffh to af0000h?afffffh 2 mb 16 128 11 sa179 to sa194 b00000h?b0ffffh to bf0000h?bfffffh 2 mb 16 128 12 sa195 to sa210 c00000h?c0ffffh to cf0000h?cfffffh 2 mb 16 128 13 sa211 to sa226 d00000h?d0ffffh to df0000h?dfffffh 2 mb 16 128 14 sa227 to sa242 e00000h?e0ffffh to ef0000h?efffffh 2 mb 15 128 15 sa243 to sa257 f00000h?f0ffffh to fe0000h?feffffh 4 32 sa258 ff0000h?ff3fffh contains four smaller sectors at top of addressable memory. sa259 ff4000h?ff7fffh sa260 ff8000h?ffbfffh sa261 ffc000h?ffffffh
22 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not exp licitly listed (such as sa005?sa009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 7.2 s29ws128n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 1 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. 32 sa001 004000h?007fffh 32 sa002 008000h?00bfffh 32 sa003 00c000h?00ffffh 7 128 sa004 to sa010 010000h?01ffffh to 070000h?07ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. ( see note ) 1 mb 8 128 1 sa011 to sa018 080000h?08ffffh to 0f0000h?0fffffh 1 mb 8 128 2 sa019 to sa026 100000h?10ffffh to 170000h?17ffffh 1 mb 8 128 3 sa027 to sa034 180000h?18ffffh to 1f0000h?1fffffh 1 mb 8 128 4 sa035 to sa042 200000h?20ffffh to 270000h?27ffffh 1 mb 8 128 5 sa043 to sa050 280000h?28ffffh to 2f0000h?2fffffh 1 mb 8 128 6 sa051 to sa058 300000h?30ffffh to 370000h?37ffffh 1 mb 8 128 7 sa059 to sa066 380000h?38ffffh to 3f0000h?3fffffh 1 mb 8 128 8 sa067 to sa074 400000h?40ffffh to 470000h?47ffffh 1 mb 8 128 9 sa075 to sa082 480000h?48ffffh to 4f0000h?4fffffh 1 mb 8 128 10 sa083 to sa090 500000h?50ffffh to 570000h?57ffffh 1 mb 8 128 11 sa091 to sa098 580000h?58ffffh to 5f0000h?5fffffh 1 mb 8 128 12 sa099 to sa106 600000h?60ffffh to 670000h?67ffffh 1 mb 8 128 13 sa107 to sa114 680000h?68ffffh to 6f0000h?6fffffh 1 mb 8 128 14 sa115 to sa122 700000h?70ffffh to 770000h?77ffffh 1 mb 7 128 15 sa123 to sa129 780000h?78ffffh to 7e0000h?7effffh 4 32 sa130 7f0000h?7f3fffh contains four smaller sectors at top of addressable memory. 32 sa131 7f4000h?7f7fffh 32 sa132 7f8000h?7fbfffh 32 sa133 7fc000h?7fffffh
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 23 advance information note: this table has been condensed to show sector-related information for an entire device on a single page. sectors and their address ranges that are not exp licitly listed (such as sa008?sa009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. for example, all 128 kb sectors have the pattern xx00000h?xxffffh. table 7.3 s29ws064n sector & memory address map bank size sector count sector size (kb) bank sector/ sector range address range notes 0.5 mb 4 32 0 sa000 000000h?003fffh contains four smaller sectors at bottom of addressable memory. sa001 004000h?007fffh sa002 008000h?00bfffh sa003 00c000h?00ffffh 3 128 sa004 010000h?01ffffh all 128 kb sectors. pattern for sector address range is xx0000h?xxffffh. (see note) sa005 020000h?02ffffh sa006 030000h?03ffffh 0.5 mb 4 128 1 sa007?sa010 040000h?04ffffh to 070000h?07ffffh 0.5 mb 4 128 2 sa011?sa014 080000h?08ffffh to 0b0000h?0bffffh 0.5 mb 4 128 3 sa015?sa018 0c0000h?0cffffh to 0f0000h?0fffffh 0.5 mb 4 128 4 sa019?sa022 100000h?10ffffh to 130000h?13ffffh 0.5 mb 4 128 5 sa023?sa026 140000h?14ffffh to 170000h?17ffffh 0.5 mb 4 128 6 sa027?sa030 180000h?18ffffh to 1b0000h?1bffffh 0.5 mb 4 128 7 sa031?sa034 1c0000h?1cffffh to 1f0000h?1fffffh 0.5 mb 4 128 8 sa035?sa038 200000h?20ffffh to 230000h?23ffffh 0.5 mb 4 128 9 sa039?sa042 240000h?24ffffh to 270000h?27ffffh 0.5 mb 4 128 10 sa043?sa046 280000h?28ffffh to 2b0000h?2bffffh 0.5 mb 4 128 11 sa047?sa050 2c0000h?2cffffh to 2f0000h?2fffffh 0.5 mb 4 128 12 sa051?sa054 300000h?30ffffh to 330000h?33ffffh 0.5 mb 4 128 13 sa055?sa058 340000h?34ffffh to 370000h?37ffffh 0.5 mb 4 128 14 sa059?sa062 380000h?38ffffh to 3b0000h?3bffffh 0.5 mb 3 128 15 sa063 3c0000h?3cffffh sa064 3d0000h?3dffffh sa065 3e0000h?3effffh 4 32 sa066 3f0000h?3f3fffh contains four smaller sectors a t top of addressable memory. sa067 3f4000h?3f7fffh sa068 3f8000h?3fbfffh sa069 3fc000h?3fffffh
24 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 8 device operations this section describes the read, program, erase, simultaneous read/write operations, handshak- ing, and reset features of the flash devices. operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see ta b l e 1 3 . 1 and ta b l e 1 3 . 2 ). the command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the com- mand. the contents of the register serve as in put to the internal stat e machine and the state machine outputs dictate the function of the device. writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to retu rn the device to the reading array data mode. 8.1 device operation table the device must be setup appropriately for each operation. ta b l e 8 . 1 describes the required state of each control pin for any particular operation. legend: l = logic 0, h = logic 1, x = don?t care, i/o = input/output. 8.2 asynchronous read all memories require access time to output array data. in an asynchronous read operation, data is read from one memory location at a time. addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asyn- chronously with the address on its inputs. the device defaults to reading array data asynch ronously after device po wer-up or hardware re- set. asynchronous read requires that the clk signal remain at v il during the entire memory read operation. to read data from the memory array, the system must first assert a valid address on a max ?a0, while driving avd# and ce# to v il . we# must remain at v ih . the rising edge of avd# latches the address. the oe# signal must be driven to v il , once avd# has been driven to v ih . data is output on a/dq15-a/dq0 pins after the access time (t oe ) has elapsed from the falling edge of oe#. ta b l e 8 . 1 d e v i c e o p e r a t i o n s operation ce# oe# we# addresses dq15?0 reset# clk avd# asynchronous read - addresses latched l l h addr in data out h x asynchronous read - addresses steady state l l h addr in data out h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x x high z h x x hardware reset x x x x high z l x x burst read operations (synchronous) load starting burst address l x h addr in x h advance burst to next address with appropriate data presented on the data bus ll h x burst data out hh terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle lx h addr in i/o h
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 25 advance information 8.3 synchronous (burst) read mode and configuration register when a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous (or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. after an initial access time required for the data from the first address location, subseque nt data is output synchronized to a clock input provided by the system. the device offers both continuous and linear me thods of burst read operation, which are dis- cussed in sections 8.3.1 , 8.3.2 , and 8.3.3 . since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to enable the burst read mode. other configuration register settings include the number of wait states to insert before the initial word (t iacc ) of each burst access, the burst mode in which to operate, and when rdy indicates data is ready to be read. prior to entering the burst mode, the system shou ld first determine the configuration register set- tings (and read the current register settings if desired via the read configuration register command sequence), and then write the configuration register command sequence. see 8.3.4 and ta b l e 1 3 . 1 for further details. figure 8.1 synchronous/asynchronous state diagram the device outputs the initial word subject to the following operational conditions: ? t iacc specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device outputs. ? configuration register setting cr13?cr11: the total number of clock cycles (wait states) that occur before valid data appears on the device outputs. the effect is that t iacc is lengthened. the device outputs subsequent words t bacc after the active edge of each successive clock cycle, which also increments the internal address counter. the device outputs burst data at this rate sub- ject to the following operational conditions: power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (cr15 = 0) set burst mode configuration register command for asynchronous mode (cr15 = 1)
26 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information ? starting address: whether the address is divisible by four (where a[1:0] is 00). a divisible- by-four address incurs the least number of additional wait states that occur after the initial word. the number of additional wait states re quired increases for burst operations in which the starting address is one, two, or three loca tions above the divisible-by-four address (i.e., where a[1:0] is 01, 10, or 11). ? boundary crossing: there is a boundary at every 128 words due to the internal architecture of the device. one additional wait state must be inserted when crossing this boundary if the memory bus is operating at a high clock freq uency. please refer to the tables below. ? clock frequency: the speed at which the device is expected to burst data. higher speeds require additional wait states after the initial word for proper operation. in all cases, with or without latency, the rdy output indicates when the next data is available to be read. ta b l e s 8.2 ? 8.6 reflect wait states required for s29w s256/128/064n device s. refer to the con- figuration register table (cr11 ? cr14) and timing diagrams for more details. table 8.2 address latency (s29ws256n) word wait states cycle 0 x ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 x ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 x ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 x ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 table 8.3 address latency (s29ws128n/s29ws064n) word wait states cycle 0 5, 6, 7 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5, 6, 7 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 5, 6, 7 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 5, 6, 7 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 table 8.4 address/boundary crossing latency (s29ws256n @ 80/66 mhz) word wait states cycle 0 7, 6 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 7, 6 ws d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 7, 6 ws d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 7, 6 ws d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 27 advance information table 8.5 address/boundary crossi ng latency (s29ws256n @ 54mhz) word wait states cycle 0 5 ws d0 d1 d2 d3 d4 d5 d6 d7 d8 1 5 ws d1 d2 d3 1 ws d4 d5 d6 d7 d8 2 5 ws d2 d3 1 ws 1 ws d4 d5 d6 d7 d8 3 5 ws d3 1 ws 1 ws 1 ws d4 d5 d6 d7 d8 ta b l e 8 . 6 address/boundary crossing latency (s29ws128n/s29ws064n) word wait states cycle 0 5, 6, 7 ws d0 d1 d2 d3 1 ws d4 d5 d6 d7 1 5, 6, 7 ws d1 d2 d3 1 ws 1 ws d4 d5 d6 d7 2 5, 6, 7 ws d2 d3 1 ws 1 ws 1 ws d4 d5 d6 d7 3 5, 6, 7 ws d3 1 ws 1 ws 1 ws 1 ws d4 d5 d6 d7
28 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information figure 8.2 synchronous read 8.3.1 continuous burst read mode in the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to address 000000h when it reaches the highest addressable memory location. the burst read mode continues until the system drives ce# high, or reset= v il . continuous burst mode can also be aborted by asserting avd# low and providing a new ad- dress to the device. if the address being read crosses a 128-word line boundary (as mentioned above) and the sub- sequent word line is not being programmed or erased, additional latency cycles are required as reflected by the configuration register table ( ta b l e 8 . 8 ). if the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. upon completion of status read or program or erase operation, the host can restart a burst read operation using a new ad- dress and avd# pulse. write unlock cycles: address 555h, data aah address 2aah, data 55h write set configuration register command and settings: address 555h, data d0h address x00h, data cr load initial address address = ra read initial data rd = dq[15:0] read next data rd = dq[15:0] wait t iacc + programmable wait state setting wait x clocks: additional latency due to starting address, clock frequency, and boundary crossing end of data? yes crossing boundary? no yes completed delay x clocks unlock cycle 1 unlock cycle 2 ra = read address rd = read data command cycle cr = configuration register bits cr15-cr0 cr13-cr11 sets initial access time (from address latched to valid data) from 2 to 7 clock cycles note: setup configuration register parameters
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 29 advance information 8.3.2 8-, 16-, 32-word linear burst read with wrap around in a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from con- secutive addresses that are determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see ta b l e 8 . 7 ). for example, if the starting address in the 8-word mode is 3ch, the address range to be read would be 38-3fh, and the burst sequence would be 3c-3d-3e-3f-38-39-3a-3bh. thus, the device outputs all words in that burst address group until all word are read, regardless of where the start- ing address occurs in the address group, and then terminates the burst read. in a similar fashion, the 16-word and 32-word li near wrap modes begin th eir burst sequence on the starting address provided to the device, then wrap back to the first address in the selected address group. note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states are inserted due to boundary crossing. 8.3.3 8-, 16-, 32-word linear burst without wrap around if wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum memory addres s of the selected number of words. the burst stops after 8, 16, or 32 addresses and does not wrap around to the first address of the selected group. for example, if the starting address in the 8- word mode is 3ch, the address range to be read would be 39-40h, and the burst sequence would be 3c-3d-3e-3f-40-41-42-43h if wrap around is not enabled. the next address to be read requires a new address and avd# pulse. note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which will incur the additional boundary crossing wait state. 8.3.4 configuration register the configuration register sets various operational parameters associated with burst mode. upon power-up or hardware re set, the device defaults to the asynchronous read mode, and the config- uration register settings are in their default state. the host system should determine the proper settings for the entire configuration register, an d then execute the set configuration register command sequence, before attempting burst operations. the configuration register is not reset after deasserting ce#. the configuration register can also be read using a command sequence (see ta b l e 1 3 . 1 ). the following list describes the register settings. table 8.7 burst address groups mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
30 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information reading the configuration table. the configuration register can be read with a four-cycle com- mand sequence. see table 13.1 for sequence details. once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. 8.4 autoselect the autoselect is used for manufacturer id, device identification, and sector protection informa- tion. this mode is primarily intended for programming equipment to automatically match a device with its corresponding programming algorithm. the autoselect codes can also be accessed in-sys- tem. when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 8 . 9 ). the remaining address bits are don't care. the most significant four bits of the address during the third write cycle selects the bank from which the autoselect codes are read by the host. all other banks can be accessed normally for data read without exiting the autoselect mode. ? to access the autoselect codes, the host system must issue the autoselect command. table 8.8 configuration register cr bit function settings (binary) cr15 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous read mode (default) enabled cr14 boundary crossing 54 mhz 66 mhz 80 mhz s29ws064n s29ws128n n/a n/a n/a default value is 0 s29ws256n 0 1 1 0 = no extra boundary crossing latency 1 = with extra boundary crossing latency (default) must be set to 1 greater than 54 mhz. cr13 programmable wait state s29ws064n s29ws128n 011 011 = data valid on 5th active clk edge after addresses latched 100 = data valid on 6th active clk edge after addresses latched 101 = data valid on 7th active clk edge after addresses latched (default) 110 = reserved 111 = reserved inserts wait states before initial data is available. setting greater number of wait states before initial data reduces latency after initial data. (notes 1 , 2 ) s29ws256n cr12 s29ws064n s29ws128n 100 s29ws256n cr11 s29ws064n s29ws128n 101 s29ws256n cr10 rdy polarity 0 = rdy signal active low 1 = rdy signal active high (default) cr9 reserved 1 = default cr8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) when cr13-cr11 are set to 000, rdy is active with data regardless of cr8 setting. cr7 reserved 1 = default cr6 reserved 1 = default cr5 reserved 0 = default cr4 reserved 0 = default cr3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr2 cr1 cr0 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) notes: 1. refer to tables 8.2 - 8.6 for wait states requirements. 2. refer to synchronous burst read timing diagrams 3. configuration register is in the default state upon power-up or hardware reset.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 31 advance information ? the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing. autoselect does not support simultaneous operations or burst mode. ? the system must write the reset command to return to the read mode (or erase-suspend- read mode if the bank was previously in erase suspend). see ta b l e 1 3 . 1 for command sequence details. table 8.9 autoselect addresses description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 2230 (ws256n) 2231 (ws128n) 2232 (ws064n) device id, word 3 (ba) + 0fh 2200 indicator bits ( see note ) (ba) + 03h dq15 - dq8 = reserved dq7 (factory lock bit): 1 = locked, 0 = not locked dq6 (customer lock bit): 1 = locked, 0 = not locked dq5 (handshake bit): 1 = reserved, 0 = standard handshake dq4, dq3 (wp# protection boot code): 00 = wp# protects both top boot and bottom boot sectors. 01, 10, 11 = reserved dq2 = reserved dq1 (dyb power up state [lock register dq4]): 1 = unlocked (user option), 0 = locked (default) dq0 (ppb eraseability [lock register dq3]): 1 = erase allowed, 0 = erase disabled sector block lock/ unlock (sa) + 02h 0001h = locked, 0000h = unlocked note: for ws128n and ws064, dq1 and dq0 are reserved.
32 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. any offset within the device works. 2. ba = bank address. the bank address is required. 3. base = base address. the following is a c source code example of using the autoselect function to read the manu- facturer id. refer to the spansion low level driver user guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software develop- ment guidelines. /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *( (uint16 *)bank_addr + 0x000 ); /* read manuf. id */ /* autoselect exit */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* exit autoselect (write reset command) */ software functions and sample code ta b l e 8 . 1 0 autoselect entry (lld function = lld_autoselectentrycmd) cycle operation byte address word address data unlock cycle 1 write baxaaah bax555h 0x00aah unlock cycle 2 write bax555h bax2aah 0x0055h autoselect command write baxaaah bax555h 0x0090h ta b l e 8 . 1 1 autoselect exit (lld function = lld_autoselectexitcmd) cycle operation byte address word address data unlock cycle 1 write base + xxxh base + xxxh 0x00f0h
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 33 advance information 8.5 program/erase operations these devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. however, prior to any programming and or erase op- eration, devices must be setup appropriately as outlined in the configuration register ( ta b l e 8 . 8 ). for any program and or erase operations, including writing command sequences, the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or programming data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. note the following: ? when the embedded program algorithm is comple te, the device return s to the read mode. ? the system can determine the status of the pr ogram operation by using dq7 or dq6. refer to the write operation status section for information on these status bits. ? a 0 cannot be programmed back to a 1 . attempting to do so causes the device to set dq5 = 1 (halting any further operation and requiring a reset command). a succeeding read shows that the data is still 0. only erase operations can convert a 0 to a 1 . ? any commands written to the device during the embedded program algorithm are ignored except the program suspend command. ? secured silicon sector, autoselect, and cfi fu nctions are unavailable when a program oper- ation is in progress. ? a hardware reset immediately terminates th e program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming is allowed in any sequence and across sector boundaries for single word pro- gramming operation. 8.5.1 single word programming single word programming mode is the simplest method of programmi ng. in this mode, four flash command write cycles are used to program an individual flash address. the data for this pro- gramming operation could be 8-, 16- or 32-bits wide. while this method is supported by all spansion devices, in general it is not recommended for devices that support write buffer pro- gramming. see ta b l e 1 3 . 1 for the required bus cycles and figure 8.3 for the flowchart. when the embedded program algorithm is complete , the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program oper- ation by using dq7 or dq6. refer to the write op eration status section for information on these status bits. ? during programming, any command (except the suspend program command) is ignored. ? the secured silicon sector, autoselect, and cfi functions are unavailable when a program op- eration is in progress. ? a hardware reset immediately terminates the program operation. the program command se- quence should be reinitiated once the device ha s returned to the read mode, to ensure data integrity.
34 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information figure 8.3 single word program write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 35 advance information note: base = base address. the following is a c source code example of using the single word program function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll for program completion */ 8.5.2 write buffer programming write buffer programming allows the system to write a maximum of 32 words in one program- ming operation. this results in a faster effective word programming time than the standard word programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming occurs. at this point, the system writes the number of word locations minus 1 that are loaded into the page buffer at the sector address in which programming occurs. this tells the device how many write buffer addresses are loaded with data and therefore when to expect the program buffer to flash confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. (number loaded = the number of locations to program minus 1 . for example, if the sys- tem programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. all subsequent address/data pairs must fall within the elected-write-buffer-page. the write-buffer-page is selected by using the addresses a max - a5. the write-buffer-page addresses must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer- pages . this also means that write buffer programming cannot be performed across multiple sec- tors. if the system attempts to load programming data outside of the selected write-buffer-page , the operation aborts.) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffer address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. also, the last data loaded at a location before the program buffer to flash confirm command is programmed into th e device. it is the software's re- sponsibility to comprehend ramifications of loading a write-buffer location more than once. the software functions and sample code ta b l e 8 . 1 2 single word program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word
36 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information counter decrements for each data load operation, not for each unique write-buffer-address loca- tion. once the specified number of write buffer loca tions have been loaded, the system must then write the program buffer to flash command at the sector ad dress. any other address/data write combinations abort the write buffer programming operation. the device goes busy . the data bar polling techniques should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an ad dress in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer embedded programming operation can be suspended using the standard sus- pend/resume commands. upon successful completion of the write buffer programming operation, the device returns to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is greater than the page buffer size during the number of locations to pro- gram step . ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different wr ite-buffer-page than the one selected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded ), dq6 = toggle, dq5 = 0. this indicates that the write buffer programming operation was aborted. a write-to-buffer-abort reset command sequence is requ ired when using the write buffer programming features in unlock bypass mode. note that the secured silicon sector, au- toselect, and cfi functions are unavailable when a program operation is in progress. write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. use of the write buffer is strongly recommended for programming when multiple words are to be programmed. write buffer programming is approxim ately eight times faster than programming one word at a time.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 37 advance information notes: 1. base = base address. 2. last = last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. for maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (n words) possible. the following is a c source code example of u sing the write buffer program function. refer to the spansion low level driver user guide (available on www.amd.com and www.fujitsu.com m) for general information on spansion flash memory software develop- ment guidelines. /* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0025; /* write write buffer load command */ *( (uint16 *)sector_address ) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *( (uint16 *)sector_address ) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *( (uint16 *)addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)addr + 0x555 ) = 0x00f0; /* write buffer abort reset */ software functions and sample code table 8.13 write buffer program (lld functions used = lld_writetobu ffercmd, lld_programbuffertoflashcmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 write buffer load command write program address 0025h 4 write word count write program address word count (n?1)h number of words (n) loaded into the write buffer can be from 1 to 32 words. 5 to 36 load buffer word n write program address, word n word n last write buffer to flash write sector address 0029h
38 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information figure 8.4 write buffer programming operation 8.5.3 sector erase the sector erase function erases one or more sectors in the memory array. (see ta b l e 1 3 . 1 and figure 8.5 ) the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pat- tern prior to electrical erase. after a successful sector erase, all locations within the erased sector contain ffffh. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than t sea occurs. dur- ing the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than t sea . write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes yes no no no no no wc = 0? write buffer abort desired? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. write to a different sector address to cause write buffer abort pass. device is in read mode. confirm command: sa 29h wait 4 s perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 39 advance information any sector erase address and command following the exceeded time-out (t sea ) may or may not be accepted. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system can monitor dq3 to determine if the sector erase timer has timed out (see dq3: sector erase timeout state indicator ). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and ad- dresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing banks. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. see write operation status for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a ha rdware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 8.5 illustrates the algorithm for the erase operation. see erase/program timing for param- eters and timing diagrams. the following is a c source code example of using the sector erase function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: sector erase command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)sector_address ) = 0x0030; /* write sector erase command */ software functions and sample code ta b l e 8 . 1 4 sector erase (lld function = lld_sectorerasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 sector erase command write sector address sector address 0030h unlimited additional sectors may be selected for erase; command(s) must be written within t sea .
40 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. see table 13.1 for erase command sequence. 2. see the section on dq3 for informat ion on the sector erase timeout. figure 8.5 sector erase operation no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? each additional cycle must be written within t sea timeout timeout resets after each additional cycle is written the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands no limit on number of sectors commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 41 advance information 8.5.4 chip erase command sequence chip erase is a six-bus cycle operation as indicated by ta b l e 1 3 . 1 . these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprogram s and verifies the entire memory for an all zero data pattern prior to electrical erase. after a successful chip erase, all locations of the chip contain ffffh. the system is not required to pr ovide any controls or timings during these oper- ations. ta b l e 1 3 . 1 and ta b l e 1 3 . 2 in the appendix show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and ad- dresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. see write operation status for information on these status bits. any commands written during the chip erase operat ion are ignored. however, note that a hard- ware reset immediately terminates the erase oper ation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the following is a c source code example of using the chip erase function. refer to the span- sion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash me mory software development guidelines. /* example: chip erase command */ /* note: cannot be suspended */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write additional unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write additional unlock cycle 2 */ *( (uint16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */ 8.5.5 erase suspend/er ase resume commands when the erase suspend command is written during the sector erase time-out, the device imme- diately terminates the time-out period and su spends the erase operation. the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the min- imum t sea time-out period during the sector er ase command sequence. the erase suspend command is ignored if written du ring the chip erase operation. when the erase suspend command is written after the t sea time-out period has expired and dur- ing the sector erase operation, the device requires a maximum of t esl (erase suspend latency) to suspend the erase operation. software functions and sample code ta b l e 8 . 1 5 c h i p e r a s e (lld function = lld_chiperasecmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 setup command write base + aaah base + 555h 0080h 4 unlock write base + aaah base + 555h 00aah 5 unlock write base + 554h base + 2aah 0055h 6 chip erase command write base + aaah base + 555h 0010h
42 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the de- vice erase suspends all sectors selected for erasure.) reading at any address within erase- suspended sectors produces status information on dq7-dq0. the system can use dq7, or dq6, and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to table 8.23 for information on these status bits. after an erase-suspended program operation is co mplete, the bank returns to the erase-suspend- read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. in the erase-suspend-read mode, the system ca n also issue the autoselect command sequence. see write buffer programming and autoselect for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is requ ired when writing this command. further writes of the resume command are ignored. another er ase suspend command can be written after the chip has resumed erasing. the following is a c source code example of using the erase suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: erase suspend command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of using the erase resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: erase resume command */ *( (uint16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ 8.5.6 program suspend/pr ogram resume commands the program suspend command allows the system to interrupt an embedded programming op- eration or a write to buffer programming operation so that data can read from any non- suspended sector. when the program suspend command is written during a programming pro- cess, the device halts the programming operation within t psl (program suspend latency) and updates the status bits. addresses are don't-cares when writing the program suspend command. software functions and sample code ta b l e 8 . 1 6 erase suspend (lld function = lld_erasesuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h ta b l e 8 . 1 7 erase resume (lld function = lld_eraseresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 43 advance information after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a program- ming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in program sus- pend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device re- verts to program suspend mode, and is re ady for another valid operation. see autoselect for more information. after the program resume command is written, the device reverts to programming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume command (address bits are don't care ) to exit the program suspend mode and continue the programmi ng operation. further writes of the program resume command are ignored. another program suspend command can be written after the de- vice has resumed programming. the following is a c source code example of using the program suspend function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program suspend command */ *( (uint16 *)base_addr + 0x000 ) = 0x00b0; /* write suspend command */ the following is a c source code example of using the program resume function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: program resume command */ *( (uint16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */ 8.5.7 accelerated pr ogram/chip erase accelerated single word programming, write buffe r programming, sector erase, and chip erase operations are enabled through the acc function. th is method is faster than the standard chip program and erase command sequences. the accelerated chip program and erase functions must not be used more than 10 times per sector. in addition, accelerated chip program and erase should be performed at room tem- perature (25 c 10 c). software functions and sample code ta b l e 8 . 1 8 program suspend (lld function = lld_programsuspendcmd) cycle operation byte address word address data 1 write bank address bank address 00b0h ta b l e 8 . 1 9 program resume (lld function = lld_programresumecmd) cycle operation byte address word address data 1 write bank address bank address 0030h
44 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information if the system asserts v hh on this input, the device automatically enters the aforementioned un- lock bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. the system can then use the write buffer load command se- quence provided by the unlock bypass mode. note that if a write-to-buffer-abort reset is required while in unlock bypass mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded pro- gram or erase operation, returns the device to normal operation. ? sectors must be unlocked prior to raising acc to v hh . ? the acc pin must not be at v hh for operations other than accelerated programming and ac- celerated chip erase, or device damage may result. ? the acc pin must not be left floating or unconne cted; inconsistent behavior of the device may result. ? acc locks all sector if set to v il . acc should be set to v ih for all other conditions. 8.5.8 unlock bypass the device features an unlock bypass mode to facilitate faster word programming. once the de- vice enters the unlock bypass mode, only two write cycles are required to program data, instead of the normal four cycles. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. see the appendix for the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 45 advance information the following are c source code examples of u sing the unlock bypass entry, program, and exit functions. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujitsu.com ) for general information on spansion flash ?memory software development guidelines. /* example: unlock bypass entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)bank_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *( (uint16 *)bank_addr + 0x555 ) = 0x00a0; /* write program setup command */ *( (uint16 *)pa ) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; 8.5.9 write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling. the data# polling bit, dq7, indicates to the host system whether an em- bedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command se- software functions and sample code ta b l e 8 . 2 0 unlock bypass entry (lld function = lld_unlockbypassentrycmd) cycle description operation byte address word address data 1 unlock write base + aaah base + 555h 00aah 2 unlock write base + 554h base + 2aah 0055h 3 entry command write base + aaah base + 555h 0020h table 8.21 unlock bypass program (lld function = lld_unlockbypassprogramcmd) cycle description operation byte address word address data 1 program setup command write base + xxxh base +xxxh 00a0h 2 program command write program address program address program data table 8.22 unlock bypass reset (lld function = lld_unlockbypassresetcmd) cycle description operation byte address word address data 1 reset cycle 1 write base + xxxh base +xxxh 0090h 2 reset cycle 2 write base + xxxh base +xxxh 0000h
46 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information quence. note that the data# polling is valid only for the last word being programmed in the write- buffer-page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the writ e-buffer-page returns false status information. during the embedded program algorithm, the de vice outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is comple te, the device outputs the datum programmed to dq7. the system must provide the program addr ess to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approxi- mately t psp , then that bank returns to the read mode. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling pro- duces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately t asp , then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asyn- chronously with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 appears on successive read cycles. see the following for more information: table 8.23 , write operation status , shows the outputs for data# polling on dq7. figure 8.6 , write operation status flowchart , shows the data# polling algorithm; and figure 12.17 , data# polling timings (during embedded algorithm) , shows the data# polling timing diagram.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 47 advance information figure 8.6 write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1) dq6 is toggling if read2 dq6 does not equal read3 dq6. 2) dq2 is toggling if read2 dq2 does not equal read3 dq2. 3) may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4) write buffer error if dq1 of last read =1. 5) invalid state, use reset command to exit operation. 6) valid data is the data that is intended to be programmed or all 1's for an erase operation. 7) data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
48 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information dq6: toggle bit i . toggle bit i on dq6 indicates whether an embedded program or erase algo- rithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (pri or to the program or erase operation), and dur- ing the sector erase time-out. during an embedded program or erase algorith m operation, successive read cycles to any ad- dress cause dq6 to toggle. when the oper ation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately t asp [all sectors protected toggle time], then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to dete rmine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog- gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protec ted sector, dq6 toggles for approximately t pap after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed- ded program algorithm is complete. see the following for additional information: figure 8.6 , write operation status flowchart ; figure 12.18 , toggle bit timings (dur ing embedded algorithm) , and ta b l e 8 . 2 3 and ta b l e 8 . 2 4 . toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. dq2: toggle bit ii . the toggle bit ii on dq2, when used with dq 6, indicates whether a partic- ular sector is actively erasing (that is, the embe dded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 ca nnot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 8.23 to compare outputs for dq2 and dq6. see the follo wing for additional information: figure 8.6 , the dq6: tog- gle bit i section, and figures 12.17 ? 12.20 . reading toggle bits dq6/dq2. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typ- ically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erases operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bi t is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then deter- mine again whether the toggle bit is toggling, sin ce the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the rese t command to return to reading array data. the remaining scenario is that the system initially de termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through succes- sive read cycles, determining the status as describe d in the previous paragr aph. alternatively, it
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 49 advance information may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 8.6 for more details. dq5: exceeded timing limits. dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that the program or erase cycle was not successful ly completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a 1. under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timeout state indicator. after writing a sector erase command sequence, the system may read dq3 to de termine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each addi tional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1. if the time between additional sector erase commands from the system can be assumed to be less than t sea , the system need not monitor dq3. see sector erase command sequence for more details. after the sector erase command is written, the syst em should read the status of dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure that th e device has accepted the command sequence, and then read dq3. if dq3 is 1 , the embedded erase algorithm ha s begun; all further commands (ex- cept erase suspend) are ignored until the erase operation is complete. if dq3 is 0 the device accepts additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each sub-sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 8.23 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort. dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a 1 . the system must issue the write to buffer abort reset command sequence to return the device to reading array data. see write buffer programming operation for more details. ta b l e 8 . 2 3 write operation status notes: 1. dq5 switches to 1 when an embedded program or embedd ed erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer pr ogramming operations. note that dq7# during write buffer pro gramming indicates the data-bar for dq7 data for the last loaded write-buffer address location . program suspend mode ( note 3 ) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data write to buffer ( note 5 ) busy state dq7# to gg l e 0 n/a n/a 0 exceeded timing limits dq7# to gg l e 1 n/a n/a 0 abort state dq7# to gg l e 0 n/a n/a 1
50 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 8.6 simultaneous read/write the simultaneous read/write feature allows the host system to read data from one bank of mem- ory while programming or erasing another bank of memory. an erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). figure 12.24 , back-to-back read/write cycle timings , shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc character- istics table for read-while-program and re ad-while-erase current specification. 8.7 writing commands/command sequences when the device is configured for asynchronous read, only asynchronous write operations are allowed, and clk is ignored. when in the synchronou s read mode configuratio n, the device is able to perform both asynchronous and synchronous write operations. clk and avd# induced address latches are supported in the synchronous programming mode. during a synchronous write oper- ation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asynchronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e s 7.1 ? 7.3 indicate the address space that each sector occupies. the device address space is divided into sixteen banks: banks 1 through 14 co ntain only 64 kword sectors, while banks 0 and 15 contain both 16 kword boot sectors in addition to 64 kword sectors. a bank address is the set of address bits required to uniquely select a bank. similarly, a sector address is the address bits required to uniquely select a sector. i cc2 in dc characteristics represents the active current spec- ification for the write mode. ac characteristics-synchronous and ac characteristics? asynchronous read contain timing specification tables and timing diagrams for write operations. 8.8 handshaking the handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the rdy (ready) pin, which is a dedicated output and controlled by ce#. when the device is configured to operate in sync hronous mode, and oe# is low (active), the initial word of burst data becomes available after either the falling or rising edge of the rdy pin (de- pending on the setting for bit 10 in the configuration register). it is recommended that the host system set cr13?cr11 in the configuration register to the appropriate number of wait states to ensure optimal burst mode operation (see ta b l e 8 . 8 , configuration register ). bit 8 in the configuration register allows the host to specify whether rdy is active at the same time that data is ready, or one cycle before data is ready.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 51 advance information 8.9 hardware reset the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. when reset# is held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby current is greater. reset# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the flash memory upon a system reset. see figures 12.5 and 12.12 for timing diagrams. 8.10 software reset software reset is part of the command set (see ta b l e 1 3 . 1 ) that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. when dq5 goes high during write status oper ation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if th e device was previously in erase suspend mode. 5. after any aborted operations note: base = base address. the following is a c source code example of using the reset function. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com) for general information on spansion flash memory software development guidelines. /* example: reset (software reset of flash state machine) */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; the following are additional points to consider when using the reset command: ? this command resets the banks to the read and address bits are ignored. ? reset commands are ignored once erasure ha s begun until the operation is complete. ? once programming begins, the device ignores reset commands until the operation is com- plete ? the reset command may be wri tten between the cycles in a program command sequence be- fore programming begins (prior to the third cycl e). this resets the bank to which the system was writing to the read mode. software functions and sample code ta b l e 8 . 2 4 reset (lld function = lld_resetcmd) cycle operation byte address word address data reset command write base + xxxh base + xxxh 00f0h
52 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information ? if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? the reset command may be also written during an autoselect command sequence. ? if a bank has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. ? if dq1 goes high during a write buffer prog ramming operation, the system must write the write to buffer abort reset command sequence to reset the device to reading array data. the standard reset command does not work during this condition. ? to exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset com- mand sequence [see command table for details].
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 53 advance information 9 advanced sector protection/unprotection the advanced sector protection/unprotection feat ure disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware meth- ods, which are independent of each other. th is section describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 9.1 . figure 9.1 advanced sector protection/unprotection hardware methods software methods acc = v il ( all sectors locked) wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (ppb) 6,7,8 6. 0 = sector protected, 1 = sector unprotected. 7. protect effective only if ppb lock bit is unlocked and corresponding ppb is ?1? (unprotected). 8. volatile bits: defaults to user choice upon power-up (see ordering options). 4. 0 = sector protected, 1 = sector unprotected. 5. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 3. n = highest address sector.
54 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 9.1 lock register as shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the dyb ordering option. the device programmer or host system must then choose which sector protection method to use. program- ming (setting to 0 ) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: ? lock register persistent protection mode lock bit (dq1) ? lock register password protection mode lock bit (dq2) for programming lock register bits refer to ta b l e 1 3 . 2 . notes 1. if the password mode is chosen, the password must be programmed before setting the cor- responding lock register bit. 2. after the lock register bits command set en try command sequence is written, reads and writes for bank 0 are disabled, while reads from other banks are allowed until exiting this mode. 3. if both lock bits are selected to be progra mmed (to zeros) at the same time, the operation aborts. 4. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the protection schem e are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a sector protection method, each sector can operate in any of the following three states: 1. constantly locked. the selected sectors are protected and can not be reprogrammed unless ppb lock bit is cleared via a password, hardware reset, or power cycle. 2. dynamically locked. the selected sectors are protected and can be altered via software commands. 3. unlocked. the sectors are unprotected and can be erased and/or programmed. these states are controlled by the bit types described in sections 9.2 ? 9.6 . 9.2 persistent protection bits the persistent protection bits are unique and nonvolatile for each sector and have the same en- durances as the flash memory. pr eprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. table 9.1 lock register device dq15-05 dq4 dq3 dq2 dq1 dq0 s29ws256n 1 1 1 password protection mode lock bit persistent protection mode lock bit customer secured silicon sector protection bit s29ws128n/ s29ws064n undefined dyb lock boot bit 0 = sectors power up protected 1 = sectors power up unprotected ppb one-time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 55 advance information notes 1. each ppb is individually programmed and all are erased in parallel. 2. while programming ppb for a sector, array data can be read from any other bank, except bank 0 (used for data# polling) and the bank in which sector ppb is being programmed. 3. entry command disables reads and writes for the bank selected. 4. reads within that bank return the ppb status for that sector. 5. reads from other banks are allowed while writes are not allowed. 6. all reads must be performed using the asynchronous mode. 7. the specific sector address (a23-a14 ws256n, a22-a14 ws128n, a21-a14 ws064n) are written at the same time as the program command. 8. if the ppb lock bit is set, the ppb progra m or erase command does not execute and times- out without programming or erasing the ppb. 9. there are no means for individually erasing a sp ecific ppb and no specif ic sector address is required for this operation. 10. exit command must be issued after the execut ion which resets the device to read mode and re-enables reads and writes for bank 0 11. the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device as describ ed by the flow chart shown in figure 9.2.
56 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information figure 9.2 ppb program/erase algorithm 9.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dybs only control the protection scheme for unprotected sectors that have their ppbs cleared (erased to 1 ). by issuing the dyb set or clear command sequences, the dybs are set (pro- grammed to 0 ) or cleared (erased to 1 ), thus placing each sector in the protected or unprotected state respectively. this feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. read byte twice addr = sa0 enter ppb command set. addr = ba program ppb bit. addr = sa dq5 = 1? yes yes yes no no no yes dq6 = toggle? dq6 = toggle? read byte. addr = sa pass fail issue reset command exit ppb command set dq0 = '1' (erase) '0' (pgm.)? read byte twice addr = sa0 no wait 500 s
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 57 advance information notes 1. the dybs can be set (programmed to 0 ) or cleared (erased to 1 ) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to 1 ) and upon power up or reset, the dybs can be set or cleared depend ing upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to 1 ), then the sectorsmay be modified depending upon the ppb state of that sector (see ta b l e 9 . 2 ). 3. the sectors would be in the protected state if the option to set the dybs after power up is chosen (programmed to 0 ). 4. it is possible to have sectors that are persiste ntly locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. however, if there is a need to change the status of the per- sistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired setting s. setting the ppb lock bit once again locks the ppbs, and the device op erates normally again. 6. to achieve the best protection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when acc = v hh as they do when acc =v ih . 9.4 persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set (programmed to 0 ), it locks all ppbs and when cleared (programmed to 1 ), allows the ppbs to be changed. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit unless the device is in the password pro- tection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to 0 ) only after all ppbs are configured to the desired settings. 9.5 password protection method the password protection method allows an even higher level of security than the persistent sector protection mode by requiring a 64 bit password for unlocking the device ppb lock bit. in addition to this password requirement, after powe r up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful executio n of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications.
58 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes 1. there is no special addressing order required for programming the password. once the password is written and verified, the password mo de locking bit must be set in order to pre- vent access. 2. the password program command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0 . 3. the password is all 1 s when shipped from the factory. 4. all 64-bit password combinations are valid as a password. 5. there is no means to verify what the password is after it is set. 6. the password mode lock bit, once set, prev ents reading the 64-bit password on the data bus and further password programming. 7. the password mode lock bit is not erasable. 8. the lower two address bits (a1?a0) are valid during the password read, password program, and password unlock. 9. the exact password must be entered in or der for the unlocking function to occur. 10. the password unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. password verification is only allowed during the password programming operation. 13. all further commands to the password region are disabled and all operations are ignored. 14. if the password is lost after setting the passwor d mode lock bit, there is no way to clear the ppb lock bit. 15. entry command sequence must be issued prior to any of any operation and it disables reads and writes for bank 0. reads and writes for other banks excluding bank 0 are allowed. 16. if the user attempts to program or erase a protected sector, the device ignores the com- mand and returns to read mode. 17. a program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read comm ands dyb status, ppb status, and ppb lock status to the device.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 59 advance information figure 9.3 lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock register can only be progammed once. wait 4 s pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array.
60 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 9.6 advanced sector protection software examples table 9.2 contains all possible combinations of the dyb, ppb, and ppb lock bit relating to the sta- tus of the sector. in summary, if the ppb lock bit is locked (set to 0 ), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to 1 ) through a hardware reset or power cycle. see also figure 9.1 for an overview of the advanc ed sector protection feature. 9.7 hardware data protection methods the device offers two main types of data protec tion at the sector level via hardware control: ? when wp# is at v il , the four outermost sectors are locked (device specific). ? when acc is at v il , all sectors are locked. there are additional methods by which intended or accidental erasure of any sectors can be pre- vented via hardware means. the following subsections describes these methods: 9.7.1 wp# method the write protect feature provides a hardware meth od of protecting the four outermost sectors. this function is provided by the wp# pin and ov errides the previously discussed sector protec- tion/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the outermost boot sectors. the outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. if the system asserts v ih on the wp# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp# pin must not be left floating or unconnected as inconsistent behavior of the device may result. the wp# pin must be held stable during a command sequence execution 9.7.2 acc method this method is similar to above, except it prot ects all sectors. once acc input is set to v il , all program and erase functions are disabled and hence all sectors are protected. 9.7.3 low v cc write inhibit when v cc is less than v lko , the device does not accept any writ e cycles. this prot ects data during v cc power-up and power-down. ta b l e 9 . 2 sector protection schemes unique device ppb lock bit 0 = locked 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status any sector 0 0 x protected through ppb any sector 0 0 x protected through ppb any sector 0 1 1 unprotected any sector 0 1 0 protected through dyb any sector 1 0 x protected through ppb any sector 1 0 x protected through ppb any sector 1 1 0 protected through dyb any sector 1 1 1 unprotected
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 61 advance information the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subseque nt writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 9.7.4 write pulse glitch protection noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 9.7.5 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept com- mands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up.
62 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 10 power conservation modes 10.1 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is grea tly reduced, and the outputs are placed in the high impedance state, independent of the oe# in put. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 in dc characteristics represents the standby current specification 10.2 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. stan- dard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the auto- matic sleep mode is disabled. note that a new bu rst operation is required to provide new data. i cc6 in dc characteristics represents the automatic sleep mode current specification. 10.3 hardware reset# input operation the reset# input provides a hard ware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitr y and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. 10.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 63 advance information 11 secured silicon sector flash memory region the secured silicon sector provides an extra flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. all secured silicon reads outside of the 256-word address range returns invalid data. the factory indicator bit, dq7, (at autoselect address 03h) is used to indicate whether or not the factory se- cured silicon sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secured silicon sector is locked when shipped from the factory. please note the following general conditions: ? while secured silicon sector access is enabled, simultaneous operations are allowed except for bank 0. ? on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. ? reads can be performed in the asynchronous or synchronous mode. ? burst mode reads within secured silicon sector wrap from address ffh back to address 00h. ? reads outside of sector 0 return memory array data. ? continuous burst read past the maximum address is undefined. ? sector 0 is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible wh en the device is executing an embedded pro- gram or embedded erase algorithm. 11.1 factory secured silicon sector the factory secured silicon sector is always protected when shipped from the factory and has the factory indicator bit (dq7) permanently set to a 1 . this prevents cloning of a factory locked part and ensures the security of the esn and customer code once the product is shipped to the field. these devices are available pre programmed with one of the following: ? a random, 8 word secure esn only within the factory secured silicon sector ? customer code within the customer secu red silicon sector through the spansion tm program- ming service. ? both a random, secure esn and customer code through the spansion programming service. customers may opt to have their code progra mmed through the spansion programming services. spansion programs the customer's code, with or without the random esn. the devices are then shipped from the spansion factory with the factory secured silicon sector and customer secured silicon sector permanently locked. contact your local representative for details on using spansion programming services. table 11.1 addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
64 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 11.2 customer secured silicon sector the customer secured silicon sector is typically shipped unprotected (dq6 set to 0 ), allowing customers to utilize that sector in any manner they choose. if the security feature is not required, the customer secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the customer secured silicon sector area is protected, the customer indicator bit is permanently set to 1. ? the customer secured silicon sector can be read any number of times, but can be pro- grammed and locked only once. the customer secu red silicon sector lock must be used with caution as once locked, there is no procedure available for unlocking the customer secured silicon sector area and none of the bits in th e customer secured silicon sector memory space can be modified in any way. ? the accelerated programming (acc) and unlock bypass functions are not available when pro- gramming the customer secured silicon sector, but reading in banks 1 through 15 is avail- able. ? once the customer secured silicon sector is lo cked and verified, the system must write the exit secured silicon sector region command se quence which return the device to the mem- ory array at sector 0. 11.3 secured silicon sector entry and secured silicon sector exit command sequences the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector re- gion until the system issues the four-cycle exit secured silicon sector command sequence. see command definition table [secured s ilicon sector command table, appendix table 13.1 for address and data requirements for both command sequences. the secured silicon sector entry command allows the following commands to be executed ? read customer and factory secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 65 advance information the following are c functions and source code examples of using the secured silicon sector entry, program, and exit commands. refer to the spansion low level driver user?s guide (available soon on www.amd.com and www.fujits u.com) for general information on spansion flash memory software development guidelines. note: base = base address. /* example: secsi sector entry command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0088; /* write secsi sector entry cmd */ note: base = base address. /* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ note: base = base address. /* example: secsi sector exit command */ *( (uint16 *)base_addr + 0x555 ) = 0x00aa; /* write unlock cycle 1 */ *( (uint16 *)base_addr + 0x2aa ) = 0x0055; /* write unlock cycle 2 */ *( (uint16 *)base_addr + 0x555 ) = 0x0090; /* write secsi sector exit cycle 3 */ *( (uint16 *)base_addr + 0x000 ) = 0x0000; /* write secsi sector exit cycle 4 */ software functions and sample code ta b l e 1 1 . 2 secured silicon sector entry (lld function = lld_secsisectorentrycmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h entry cycle write base + aaah base + 555h 0088h table 11.3 secured silicon sector program (lld function = lld_programcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h program setup write base + aaah base + 555h 00a0h program write word address word address data word table 11.4 secured silicon sector exit (lld function = lld_secsisectorexitcmd) cycle operation byte address word address data unlock cycle 1 write base + aaah base + 555h 00aah unlock cycle 2 write base + 554h base + 2aah 0055h exit cycle write base + aaah base + 555h 0090h
66 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 12 electrical specifications 12.1 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to + 125c voltage with respect to ground: all inputs and i/os except as noted below ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v io + 0.5 v v cc ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +2.5 v acc ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +9.5 v output short circuit current ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 12.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 12.2 . 2. minimum dc input voltage on pin acc is -0.5v. during voltage transitions, acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 12.1 . maximum dc voltage on pin acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum ra ting conditions for extended periods may affe ct device reliability. note: the content in this document is advance information for th e s29ws064n and s29ws128n. co ntent in this document is preliminary for the s29w256n. 12.2 operating ranges wireless (w) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.70 v to +1.95 v v io supply voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 v to +1.95 v (contact local sales office for v io = 1.35 to +1.70 v.) note: operating ranges define those limits between which the device functionality is guaranteed. figure 12.1 maximum negative overshoot waveform figure 12.2 maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 67 advance information 12.3 test conditions figure 12.3 te s t s e t u p note: the content in this document is advance information for the s29ws064n and s2 9ws128n. content in this document is preliminary for the s29w256n. 12.4 key to switching waveforms note: the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. 12.5 switching waveforms figure 12.4 input waveforms and measurement levels table 12.1 test specifications test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 3.0 @ 54, 66 mhz 2.5 @ 80 mhz ns input pulse levels 0.0?v io v input timing measurem ent reference levels v io /2 v output timing measurement reference levels v io /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) c l device under test v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs
68 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 12.6 v cc power-up notes: 1. v cc >= v io - 100mv and v cc ramp rate is > 1v / 100s 2. v cc ramp rate <1v / 100s, a hardware reset is required. 3. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. figure 12.5 v cc power-up diagram parameter description test setup speed unit t vcs v cc setup time min 1 ms v cc v io reset# t vcs
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 69 advance information 12.7 dc characteristics (cmos compatible) notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. v cc = v io . 3. ce# must be set high when measuring the rdy pin. 4. the i cc current listed is typically less than 3 ma/mhz, with oe# at v ih . 5. i cc active while embedded erase or embedded program is in progress. 6. device enters automatic sleep mode when addresses are stable for t acc + 20 ns. typical sleep mode current is equal to i cc3 . 7. v ih = v cc 0.2 v and v il > ?0.1 v. 8. total current during accelerate d programming is the sum of v acc and v cc currents. 9. v acc = v hh on acc input. 10. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description (notes) test conditions (notes 1 , 2 , 9 ) min ty p max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current ( 3 ) v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 54 mhz 27 54 ma 66 mhz 28 60 ma 80 mhz 30 66 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 54 mhz 28 48 ma 66 mhz 30 54 ma 80 mhz 32 60 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 32 54 mhz 29 42 ma 66 mhz 32 48 ma 80 mhz 34 54 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 54 mhz 32 36 ma 66 mhz 35 42 ma 80 mhz 38 48 ma i io1 v io non-active output oe# = v ih 20 30 a i cc1 v cc active asynchronous read current ( 4 ) ce# = v il , oe# = v ih , we# = v ih 10 mhz 27 36 ma 5 mhz 13 18 ma 1 mhz 3 4 ma i cc2 v cc active write current ( 5 ) ce# = v il , oe# = v ih , acc = v ih v acc 15a v cc 19 52.5 ma i cc3 v cc standby current ( 6 , 7 ) ce# = reset# = v cc 0.2 v v acc 15a v cc 20 40 a i cc4 v cc reset current ( 7 ) reset# = v il, clk = v il 70 150 a i cc5 v cc active current (read while write) ( 7 ) ce# = v il , oe# = v ih , acc = v ih @ 5 mhz 50 60 ma i cc6 v cc sleep current ( 7 ) ce# = v il , oe# = v ih 240a i acc accelerated program current ( 8 ) ce# = v il , oe# = v ih, v acc = 9.5 v v acc 620ma v cc 14 20 ma v il input low voltage v io = 1.8 v ?0.5 0.4 v v ih input high voltage v io = 1.8 v v io ? 0.4 v io + 0.4 v v ol output low voltage i ol = 100 a, v cc = v cc min = v io 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min = v io v io ? 0.1 v v hh voltage for accelerated program 8.5 9.5 v v lko low v cc lock-out voltage 1.0 1.4 v
70 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 12.8 ac characteristics 12.8.1 clk characterization note: the content in this document is advance information for the s29ws064n and s2 9ws128n. content in this document is preliminary for the s29w256n. figure 12.6 clk characterization 12.8.2 synchronous/burst read notes: 1. addresses are latched on the first rising edge of clk. 2. not 100% tested. 3. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description 54 mhz 66 mhz 80 mhz unit f clk clk frequency max 54 66 80 mhz t clk clk period min 18.5 15.1 12.5 ns t ch clk high time min 7.4 6.1 5.0 ns t cl clk low time t cr clk rise time max 3 3 2.5 ns t cf clk fall time parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t iacc latency max 80 ns t bacc burst access time valid clock to output delay max 13.5 11.2 9 ns t acs address setup time to clk ( note 1 )min5 4 ns t ach address hold time from clk ( note 1 )min7 6 ns t bdh data hold time from next clock cycle min 4 3 ns t cr chip enable to rdy valid max 13.5 11.2 9 ns t oe output enable to output valid max 13.5 11.2 ns t cez chip enable to high z ( note 2 )max10 ns t oez output enable to high z ( note 2 )max 10 ns t ces ce# setup time to clk min 4 ns t rdys rdy setup time to clk min 5 4 3.5 ns t racc ready access time from clk max 13.5 11.2 9 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 4 ns t avd avd# pulse min 8 ns t aoe avd low to oe# low max 38.4 ns t clk t cl t ch t cr t cf clk
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 71 advance information 12.8.3 timing diagrams notes: 1. figure shows total number of wait states set to five cycles . the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at address + 1 , address + 2 , or address + 3 , additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode. figure 12.7 clk synchronous burst mode read da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t aoe t bdh 5 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 12 3456 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr
72 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at address + 1 , address + 2 , or address + 3 , additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode with wrap around. 4. d8?df in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 4th address in range (0-f). figure 12.8 8-word linear burst with wrap around notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at address + 1 , address + 2 , or address + 3 , additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in asynchronous mode with out wrap around. 4. dc?d13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 1st address in range (c-13). figure 12.9 8-word linear burst without wrap around dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t aoe t bdh de df db 7 cycles for initial access shown. hi-z t racc 1234567 t rdys t bacc t cr d8 t racc dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df d13 hi-z t racc 1234567 t rdys t bacc t cr d10 t racc t aoe 7 cycles for initial access shown.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 73 advance information notes: 1. figure assumes 6 wait states for initial access and synchronous read. 2. the set configuration register command sequence has been written with cr8=0; device outputs rdy one cycle before valid data. figure 12.10 linear burst with rdy set one cycle before data 12.8.4 ac characterist ics?asynchronous read notes: 1. not 100% tested. 2. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t ce access time from ce# low max 80 ns t acc asynchronous access time max 80 ns t avdp avd# low time min 8 ns t aavds address setup time to rising edge of avd# min 4 ns t aavdh address hold time from rising edge of avd# min 7 6 ns t oe output enable to output valid max 13.5 ns t oeh output enable hold time read min 0 ns data# polling min 10 ns t oez output enable to high z (see note) max 10 ns t cas ce# setup time to avd# min 0 ns da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t aoe t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 123456 t rdys t bacc t cr
74 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: ra = read address, rd = read data. figure 12.11 asynchronous mode read 12.8.5 hardware reset (reset#) notes: 1. not 100% tested. 2. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. figure 12.12 reset timings parameter description all speed options unit jedec std. t rp reset# pulse width min 30 s t rh reset high time before read ( see note )min200ns t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas reset# t rp ce#, oe# t rh
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 75 advance information 12.8.6 erase/program timing notes: 1. not 100% tested. 2. asynchronous read mode allows asynchronous program operation only. synchronous read mode allows both asynchronous and synchronous program operation. 3. in asynchronous program operation timing, addresses are latched on the falling edge of we#. in synchronous program operation timing, addresses are latched on the rising edge of clk. 4. see the erase and programming performance section for more information. 5. does not include the preprogramming time. 6. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter description 54 mhz 66 mhz 80 mhz unit jedec standard t avav t wc write cycle time ( note 1 )min80ns t avwl t as address setup time (notes 2 , 3 ) synchronous min 5ns asynchronous 0 ns t wlax t ah address hold time (notes 2 , 3 ) synchronous min 9 ns asynchronous 20 t avdp avd# low time min 8 ns t dvwh t ds data setup time min 45 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t elwl t cs ce# setup time to we# min 5 ns t avsw avd# setup time to we# min 5 ns t avhw avd# hold time to we# min 5 ns t avsc avd# setup time to clk min 5 ns t avhc avd# hold time to clk min 5 ns t csw clock setup time to we# min 5 ns t wep noise pulse margin on we# max 3 ns t sea sector erase accept time-out max 50 s t esl erase suspend latency max 20 s t psl program suspend latency max 20 s t asp toggle time during sector protection typ 100 s t psp toggle time during programming within a protected sector typ 1 s
76 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information figure 12.13 chip/sector erase operation timings oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 77 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n, a21?a 14 for the ws064n) are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of th e set device read mode bit in the configuration register. figure 12.14 asynchronous program operation timings oe# ce# data addresses avd we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs t cas
78 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. in progress and complete refer to status of program operation. 3. a23?a14 for the ws256n (a22?a14 for the ws128n, a21?a 14 for the ws064n) are don?t care during command sequence unlock cycles. 4. addresses are latched on the first rising edge of clk. 5. either ce# or avd# is required to go from low to high in be tween programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 12.15 synchronous program operation timings note: use setup and hold times from conventional program operation. figure 12.16 accelerated unlock bypass programming timing oe# ce# data addresses we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw t avsc avd# ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id v il or v ih t vid t vids
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 79 advance information notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete data# polling outputs true data. figure 12.17 data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, . figure 12.18 toggle bit timings (during embedded algorithm) we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# high z t oe high z addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
80 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, . 3. rdy is active with data (d8 = 1 in the configuration register). when d8 = 0 in the configuration register, rdy is active one clock cycle before data. figure 12.19 synchronous data polling ti mings/toggle bit timings note: dq2 toggles only when read at an address within an er ase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6 figure 12.20 dq2 vs. dq6 ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 81 advance information notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before data (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device not crossing a bank in the process of performing an erase or program. 5. rdy does not go low and no additional wait states are re quired if the burst frequency is <=66 mhz and the boundary crossing bit (d14) in the configuration register is set to 0 figure 12.21 latency with boundary crossing when frequency > 66 mhz clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc
82 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. rdy(1) active with data (d8 = 1 in the configuration register). 2. rdy(2) active one clock cycle before data (d8 = 0 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device crossing a bank in the process of performing an erase or program. 5. rdy does not go low and no additional wait states are required if the burst frequency is < 66 mhz and the boundary crossing bit (d14) in the configuration register is set to 0 . figure 12.22 latency with boundary crossing into program/erase bank clk address (hex) c124 c125 c126 c127 c127 d124 d125 d126 d127 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f latency rdy(2) latency t racc t racc t racc t racc
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 83 advance information wait state configuration register setup: d13, d12, d11 = 111 ? reserved d13, d12, d11 = 110 ? reserved d13, d12, d11 = 101 ? 5 programmed, 7 total d13, d12, d11 = 100 ? 4 programmed, 6 total d13, d12, d11 = 011 ? 3 programmed, 5 total d13, d12, d11 = 010 ? 2 programmed, 4 total d13, d12, d11 = 001 ? 1 programmed, 3 total d13, d12, d11 = 000 ? 0 programmed, 2 total note: 6.figure assumes address d0 is not at an address boundary, and wait state is set to 101 figure 12.23 example of wait state insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45
84 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while check - ing the status of the program or erase operation in the busy bank. the system should read status twice to ensure valid information. figure 12.24 back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 85 advance information 12.8.7 erase and programming performance notes: 1. typical program and erase times a ssume the following conditions: 25 c, 1.8 v v cc , 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 1.70 v, 100,000 cycles. 3. typical chip programming time is cons iderably less than the maximum chip pr ogramming time listed, and is based on utilizing the write buffer. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see the appendix for further information about command definitions. 6. contact the local sales office for mini mum cycling endurance values in specific applications and op erating conditions. 7. refer to application note erase suspend/resume timing for more details. 8. word programming specification is based upon a single word programming operation not utilizing th e write buffer. 9. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter ty p ( note 1 )max ( note 2 ) unit comments sector erase time 64 kword v cc 0.6 3.5 s excludes 00h programming prior to erasure ( note 4 ) 16 kword v cc <0.15 2 chip erase time v cc 153.6 (ws256n) 77.4 (ws128n) 39.3 (ws064n) 308 (ws256n) 154 (ws128n) 78 (ws064n) s acc 130.6 (ws256n) 65.8 (ws128n) 33.4 (ws064n) 262 (ws256n) 132 (ws128n) 66 (ws064n) single word programming time ( note 8 ) v cc 40 400 s acc 24 240 effective word programming time utilizing program write buffer v cc 9.4 94 s acc 6 60 total 32-word buffer programming time v cc 300 3000 s acc 192 1920 chip programming time ( note 3 ) v cc 157.3 (ws256n) 78.6 (ws128n) 39.3 (ws064n) 314.6 (ws256n) 157.3 (ws128n) 78.6 (ws064n) s excludes system level overhead ( note 5 ) acc 100.7 (ws256n) 50.3 (ws128n) 25.2 (ws064n) 201.3 (ws256n) 100.7 (ws128n) 50.3 (ws064n)
86 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 12.8.8 bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c; f = 1.0 mhz. 3. the content in this document is advance information fo r the s29ws064n and s29ws128n. content in this document is preliminary for the s29w256n. parameter symbol parameter description te s t s e t u p ty p . max unit c in input capacitance v in = 0 5.3 6.3 pf c out output capacitance v out = 0 5.8 6.8 pf c in2 control pin capacitance v in = 0 6.3 7.3 pf
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 87 advance information 13 appendix this section contains information relating to software control or interfacing with the flash device. for additional information and assi stance regarding software, see the additional resources on page 20, or explore the web at www.amd.com and www.fujitsu.com .
88 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information table 13.1 memory array commands command sequence (notes) cycles bus cycles (notes 1?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read ( 6 )1 ra rd reset ( 7 ) 1 xxx f0 auto- select ( 8 ) manufacturer id 4 555 aa 2aa 55 [ba]555 90 [ba]x00 0001 device id ( 9 ) 6 555 aa 2aa 55 [ba]555 90 [ba]x01 227e ba+x0e data ba+x0f 2200 indicator bits ( 10 ) 4 555 aa 2aa 55 [ba]555 90 [ba]x03 data program 4 555 aa 2aa 55 555 a0 pa pd write to buffer ( 11 ) 6 555 aa 2aa 55 pa 25 pa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset ( 12 ) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase/program suspend ( 13 ) 1 ba b0 erase/program resume ( 14 ) 1 ba 30 set configuration register ( 18 ) 4 555 aa 2aa 55 555 d0 x00 cr read configuration register 4 555 aa 2aa 55 555 c6 x00 cr cfi query ( 15 ) 1 [ba]555 98 unlock bypass mode entry 3 555 aa 2aa 55 555 20 program ( 16 ) 2 xxx a0 pa pd cfi ( 16 ) 1 xxx 98 reset 2 xxx 90 xxx 00 secured silicon sector entry 3 555 aa 2aa 55 555 88 program ( 17 ) 4 555 aa 2aa 55 555 a0 pa pd read ( 17 )1 00 data exit ( 17 ) 4 555 aa 2aa 55 555 90 xxx 00 legend: x = don?t care. ra = read address. rd = read data. pa = program address. addresses latch on the rising edge of the avd# pulse or active edge of clk, whichever occurs first. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. ws256n = a23?a14; ws128n = a22?a14; ws064n = a21?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20; ws064n = a21?a18. cr = configuration register data bits d15?d0. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 8.1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. 4. address and data bits not specifie d in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 5. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 6. no unlock or command cycles required when ba nk is reading array data. 7. reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autosele ct mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. the system must provide the bank address. see autoselect section for more information . 9. data in cycle 5 is 2230 (ws256n), 2232 (ws064n), or 2231 (ws128n). 10. see table 8.9 for indicator bit values. 11. total number of cycles in the command sequence is determined by the number of words written to the write buffer. 12. command sequence resets device for next command after write- to-buffer operation. 13. system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 14. erase resume command is valid only during the erase suspend mode, and requires the bank address. 15. command is valid when device is ready to read array data or when device is in autoselect mode. address equals 55h on all future devices, but 555h for ws256n/128n/064n. 16. requires entry command sequence prior to execution. unlock bypass reset command is required to return to reading array data. 17. requires entry command sequence prior to execution. secured silicon sector exit reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. requires reset command to configure the configuration register.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 89 advance information table 13.2 sector protection commands command sequence (notes) cycles bus cycles (notes 1 ? 4 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data lock register bits command set entry ( 5 ) 3 555 aa 2aa 55 555 40 program ( 6 , 12 ) 2 xx a0 77/00 data read ( 6 )1 77 data command set exit ( 7 ) 2 xx 90 xx 00 password protection command set entry ( 5 ) 3 555 aa 2aa 55 555 60 program [0-3] ( 8 ) 2 xx a0 00 pwd[0-3] read ( 9 )4 0...00 pwd0 0...01 pwd1 0...02 pwd2 0...03 pwd3 unlock 7 00 25 00 03 00 pwd0 01 pwd1 02 pwd2 03 pwd3 00 29 command set exit ( 7 ) 2 xx 90 xx 00 non-volatile sector protection (ppb) command set entry ( 5 ) 3 555 aa 2aa 55 [ba]555 c0 ppb program ( 10 ) 2 xx a0 sa 00 all ppb erase ( 10 , 11 ) 2 xx 80 00 30 ppb status read 1 sa rd(0) command set exit ( 7 ) 2 xx 90 xx 00 global volatile sector protection freeze (ppb lock) command set entry ( 5 ) 3 555 aa 2aa 55 [ba]555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 ba rd(0) command set exit ( 7 ) 2 xx 90 xx 00 volatile sector protection (dyb) command set entry ( 5 ) 3 555 aa 2aa 55 [ba]555 e0 dyb set 2 xx a0 sa 00 dyb clear 2 xx a0 sa 01 dyb status read 1 sa rd(0) command set exit ( 7 ) 2 xx 90 xx 00 legend: x = don?t care. ra = address of the memory location to be read. pd(0) = secured silicon sector lock bit. pd(0), or bit[0]. pd(1) = persistent protection mode lo ck bit. pd(1), or bit[1], must be set to ?0? for protection while pd(2), bit[2] must be left as ?1?. pd(2) = password protection mode lock bit. pd(2), or bit[2], must be set to ?0? for protection while pd(1), bit[1] must be left as ?1?. pd(3) = protection mode otp bit. pd(3) or bit[3]. sa = sector address. ws256n = a23?a14; ws 128n = a22?a14; ws064n = a21?a14. ba = bank address. ws256n = a23?a20; ws128n = a22?a20; ws064n = a21?a18. pwd3?pwd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0), rd(1), rd(2) = dq0, dq1, or dq2 protection indicator bit. if protected, dq0, dq1, or dq2 = 0. if unprotected, dq0, dq1, dq2 = 1. notes: 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writ ing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to en ter a specific mode to enable instructions only availa ble within that mode. 6. if both the persistent protection mode locking bit and the password protection mode locking bit are set at the same time, the command operation aborts and returns the device to the default persistent sector protection mode during 2nd bus cycle. note that on all future devices, addresses equal 00h, but is currently 77h for the ws256n only. see table 9.1 and table 9.2 for explanation of lock bits. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is requ ired for reading password. 10. see figure 9.2 for details. 11. the all ppb erase command pre-progra ms all ppbs before erasure to prevent over-erasure. 12. the second cycle address for the lock register program operation is 77 for s29ws256n; however, for ws128n and ws064n this address is 00.
90 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 13.1 common flash memory interface the common flash interface (cfi) specification outlines device and host system software inter- rogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-indepen- dent, and forward- and back-ward-compatible fo r the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when th e system writes the cfi query command, 98h, to address (ba)555h any time the de vice is ready to read array data. the system can read cfi in- formation at the addresses given in tables 13.3?13.6 ) within that bank. all reads outside of the cfi address range, within the bank, returns non- valid data. reads from other banks are allowed, writes are not. to terminate reading cfi data, the system must write the reset command. the following is a c source code example of using the cfi entry and exit functions. refer to the spansion low level driver user?s guide (available on www.amd.com and www.fujitsu.com ) for general information on spansion flash memory software development guidelines. /* example: cfi entry command */ *( (uint16 *)bank_addr + 0x555 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)bank_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ for further information, please refer to the cfi specification (see jedec publications jep137-a and jesd68.01and cfi publication 100). please contact your sales office for copies of these documents. table 13.3 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 13.4 system interface string addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0006h typical timeout per single byte/word write 2 n s 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0004h max. timeout for buffer write 2 n times typical 25h 0003h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 91 advance information ta b l e 1 3 . 5 device geometry definition addresses data description 27h 0019h (ws256n) 0018h (ws128n) 0017h (ws064n) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0006h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 00fdh (ws256n) 007dh (ws128n) 003dh (ws064n) erase block region 2 information 32h 33h 34h 0000h 0000h 0002h 35h 36h 37h 38h 0003h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information table 13.6 primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number, ascii 44h 0034h minor version number, ascii 45h 0100h address sensitive unlock (bits 1-0), 0 = required, 1 = not required silicon technology (bits 5-2) 0100 = 0.11 m 46h 0002h erase suspend, 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect, 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08 = advanced sector protection 4ah 00f3h (ws256n) 007bh (ws128n) 003fh (ws064n) simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type, 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 0001h = dual boot device 50h 0001h program suspend. 00h = not supported
92 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 51h 0001h unlock bypass, 00 = not supported, 01=supported 52h 0007h secured silicon sector (customer otp area) size 2 n bytes 53h 0014h hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 0014h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend time-out maximum 2 n ns 56h 0005h program suspend time-out maximum 2 n ns 57h 0010h bank organization: x = number of banks 58h 0013h (ws256n) 000bh (ws128n) 0007h (ws064n) bank 0 region information. x = number of sectors in bank 59h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 1 region information. x = number of sectors in bank 5ah 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 2 region information. x = number of sectors in bank 5bh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 3 region information. x = number of sectors in bank 5ch 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 4 region information. x = number of sectors in bank 5dh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 5 region information. x = number of sectors in bank 5eh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 6 region information. x = number of sectors in bank 5fh 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 7 region information. x = number of sectors in bank 60h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 8 region information. x = number of sectors in bank 61h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 9 region information. x = number of sectors in bank 62h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 10 region information. x = number of sectors in bank 63h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 11 region information. x = number of sectors in bank 64h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 12 region information. x = number of sectors in bank 65h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 13 region information. x = number of sectors in bank 66h 0010h (ws256n) 0008h (ws128n) 0004h (ws064n) bank 14 region information. x = number of sectors in bank 67h 0013h (ws256n) 000bh (ws128n) 0007h (ws064n) bank 15 region information. x = number of sectors in bank table 13.6 primary vendor-specific extended query (continued) addresses data description
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 93 advance information 14 commonly used terms te r m d e f i n i t i o n acc accelerate. a special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above v cc . in some devices acc may protect all sectors when at a low voltage. a max most significant bit of the address inpu t [a23 for 256mbit, a22 for128mbit, a21 for 64mbit] a min least significant bit of the address input si gnals (a0 for all devices in this document). asynchronous operation where signal relationships are ba sed only on propagation delays and are unrelated to synchronous control (clock) signal. autoselect read mode for obtaining manufacturer and device information as well as sector protection status. bank section of the memory array consisting of multiple consecutive sectors. a read operation in one bank, can be independen t of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. boot sector smaller size sectors located at the top and or bottom of flash device address space. the smaller sector size allows for finer gra nularity control of erase and protection for code or parameters used to initiate system operation after power-on or reset. boundary location at the beginning or end of series of memory locations. burst read see synchronous read . byte 8 bits cfi common flash interface. a flash memory in dustry standard specification [jedec 137- a and jesd68.01] designed to allow a system to interrogate the flash to determine its size, type and other performance parameters. clear zero (logic low level) configuration register special purpose register which must be programmed to enable synchronous read mode continuous read synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address erase returns bits of a flash memory array to th eir default state of a logical one (high level). erase suspend/erase resume halts an erase operation to allow reading or programming in any sector that is not selected for erasure bga ball grid array package. spansion llc offers two variations: fortified ball grid array and fine-pitch ball grid array. see the spec ific package drawing or connection diagram for further details. linear read synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address . mcp multi-chip package. a method of combining in tegrated circuits in a single package by stacking multiple die of the same or different devices. memory array the programmable area of the product available for data storage. mirrorbit? technology spansion? trademarked technology for storin g multiple bits of data in the same transistor.
94 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information page group of words that may be accessed more ra pidly as a group than if the words were accessed individually. page read asynchronous read operation of several wo rds in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read. different words in the group are accessed by changing only the least significan t address lines. password protection sector protection method wh ich uses a programmable passw ord, in addition to the persistent protection method , for protection of sectors in the flash memory device . persistent protection sector protection method that uses comm ands and only the standard core voltage supply to control protection of sectors in the flash memory device. this method replaces a prior technique of requiring a 12v supply to control th e protection method. program stores data into a flash memory by selectiv ely clearing bits of the memory array in order to leave a data pattern of ones and zeros . program suspend/program resume halts a programming operation to read data from any location that is not selected for programming or erase. read host bus cycle that causes the flash to output data onto the data bus. registers dynamic storage bits for holding device cont rol information or tracking the status of an operation. secured silicon secured silicon. an area co nsisting of 256 bytes in which any word may be programmed once, and the entire area ma y be protected once from any future programming. information in this area may be programmed at the factory or by the user. once programmed and protected ther e is no way to change the secured information. this area is often used to store a software readable identification such as a serial number. sector protection use of one or more control bi ts per sector to indicate whether each sector may be programmed or erased. if the protection bit for a sector is set the embedded algorithms for program or erase ignores program or erase commands related to that sector. sector an area of the memory array in which all bi ts must be erased together by an erase operation. simultaneous operation mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operat ion may then proceed while the host immediately follows the embedded algorith m command with reading from another bank. reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. synchronous operation operation that progresses only when a timi ng signal, known as a clock, transitions between logic levels (that is, at a clock edge). versatileio? (v io ) separate power supply or voltage reference si gnal that allows the host system to set the voltage levels that the device genera tes at its data outputs and the voltages tolerated at its data inputs. unlock bypass mode that facilitates faster program time s by reducing the number of command bus cycles required to issue a write operation co mmand. in this mode th e initial two unlock write cycles, of the usual 4 cycle program command, are not required ? reducing all program commands to two bus cycles while in this mode. word two contiguous bytes (16 bits) located at an even byte boundary. a double word is two contiguous words located on a two word boundary. a quad word is four contiguous words located on a four word boundary. te r m d e f i n i t i o n
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 95 advance information wraparound special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of words, after reading the last byte or word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. write interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. the term write is often associated with writing command cycles to enter or exit a particular mode of operation. write buffer multi-word area in which multiple words may be programmed as a single operation . a write buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. write buffer programming method of writing multiple words, up to the maximum size of the write buffer, in one operation. using write buff er programming results in 8 times faster programming time than by using single word at a time programming commands. write operation status allows the host system to determine the status of a program or erase operation by reading several special purpose register bits . te r m d e f i n i t i o n
96 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information cosmoram 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) features ? asynchronous sram interface ? fast access time ?t ce = t aa = 70ns max ? 8 words page access capability ?t paa = 20ns max ? low voltage operating condition ?v dd = +1.65v to +1.95v (32m) ? +1.70v to +1.95v (64m) ? wide operating temperature ? ta = -30c to +85c ? byte control by lb# and ub# ? low power consumption ?i dda1 = 30ma max (32m), tbdma max (64m) ?i dds1 = 80ma max (32m), tbdma max (64m) ? various power down mode ? sleep, 4m-bit partial or 8m-bit partial (32m) ? sleep, 8m-bit partial or 16m-bit partial (64m)
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 97 advance information 15 pin description (32m) pin name description a 21 to a 0 address input: a 20 to a 0 for 32m, a 21 to a 0 for 64m ce1# chip enable (low active) ce2 chip enable (high active) we# write enable (low active) oe# output enable (low active) ub# upper byte control (low active) lb# lower byte control (low active) clk clock input adv# address valid input (low active) wait# wait signal output dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply v ss ground
98 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 16 cosmoram functional description 16.1 asynchronous operation (page mode) legend: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance. notes: 1. should not be kept at this logic condition longer than 1s. 2. power down mode can be entered from standby state and all dq pi ns are in high-z state. data retention depends on the selectio n of partial size. refer to the power down in the functional description for details. 3. l for address pass through and h for address latch on the rising edge of adv#. 4. oe# can be v il during write operation if the fo llowing conditions are satisfied: (1) write pulse is initiated by ce 1# (refer to ce1# controlled write timing), or cycle time of the previous operation cycle is satisfied. (2) oe# stays v il during write cycle 5. can be either v il or v ih but must be valid before read or write. 6. output is either valid or high-z depending on the level of ub# and lb# input. mode ce2 ce1# clk adv# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 wait# standby (deselect) h h x x x x x x x high-z high-z high-z output disable (note 1) hl x (note 3) h h x x note 5 high-z high-z high-z output disable (no read) x hl h h valid high-z high-z high-z read (upper byte) x h l valid high-z output valid high-z read (lower byte) x l h valid output valid high-z high-z read (word) x l l valid output valid output valid high-z page read x l/h l/h valid note 6 note 6 high-z no write x l h (note 4) h h valid invalid invalid high-z write (upper byte) x h l valid invalid input valid high-z write (lower byte) x l h valid input valid invalid high-z write (word) x l l valid input valid input valid high-z power down (note 2) l x x x x x x x x high-z high-z high-z
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 99 advance information 16.2 synchronous operation (burst mode) legend: l = v il , h = v ih , x can be either v il or v ih , ve = valid edge, pelp = positive edge of low pulse, high- z = high impedance. notes: 1. should not be kept this logic condition longer than the specified time of 8s for 32m and 4s for 64m. 2. power down mode can be entered from standby state and all dq pi ns are in high-z state. data retention depends on the selectio n of partial size. refer to the power down for details. 3. valid clock edge shall be set on either positive or negative ed ge through cr set. clk must be started and stable prior to mem ory access. 4. can be either v il or v ih except for the case the both of oe# and we# are v il . it is prohibited to bring the both of oe# and we# to v il . 5. when device is operating in we# single clock pulse control mode, we# is don?t care once write op eration is determined by we# low pulse at the beginning of write access together with addre ss latching. write suspend feature is not supported in we# single clock pulse control mode. 6. can be either v il or v ih but must be valid before read or write is determined. and once ub# and lb# inputs are determined, they must not be changed until the end of burst. 7. once valid address is determined, input address must not be changed during adv#=l. 8. if oe#=l, output is either invalid or high-z depending on the level of ub# and lb# input. if we#=l, input is invalid. if oe#= we#=h, output is high-z. 9. output is either valid or high-z depending on the level of ub# and lb# input. 10. input is either valid or invalid depe nding on the level of ub# and lb# input. 11. output is either high-z or invalid depending on the level of oe# and we# input. 12. keep the level from previous cycle exce pt for suspending on last data. refer to wait# output function for details. 13. wait# output is driv en in high level during write operation. mode ce2 ce1# clk adv# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 wait# standby (deselect) h h x x x x x x x high-z high-z high-z start address latch (note 1) l ve (note 3) pelp x (note 4) x (note 4) x (note 6) x (note 6) valid (note 7) high-z (note 8) high-z (note 8) high-z (note 11) advance burst read to next address (note 1) ve (note 3) h h l x output valid (note 9) output valid (note 9) output valid burst read suspend (note 1) ve (note 3) h high-z high-z high (note 12) advance burst write to next address (note 1) ve (note 3) l (note 5) h input valid (note 10) input valid (note 10) high (note 13) burst write suspend (note 1) ve (note 3) h (note 5) iput invalid iput invalid high (note 12) te r m i n a t e b u r s t read ve x h x high-z high-z high-z te r m i n a t e b u r s t write ve x x h high-z high-z high-z power down (note 2) l x x x x x x x x high-z high-z high-z
100 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 17 state diagrams 17.1 initial/standby state 17.2 asynchronous operation state figure 17.1 initial standby state diagram figure 17.2 asynchronous operation state diagram cr set power down standby standby power up pause time ce2=l ce2= h power down ce2=h @rp=1 ce2=l @m=0 @m=1 ce2=h @rp=0 (64m only) common state synchronous operation (burst mode) asynchronous operation (page mode) write byte control standby ce1# = l & we# = l byte control @ oe# = l read we# = l ce2 = ce1# = h output disable we# = h oe# = h ce1# = h ce1# = l ce1# = h ce1# = h oe# = l ce1# = l & oe# = l address change or byte control
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 101 advance information 17.3 synchronous operation state notes: 1. assumes all the parame ters specified in the ac characteristics are satisfied. refer to the cosmoram functional description , ac characteristics , and the timing diagrams for details. rp (reset to page ) mode is available only for 64m. figure 17.3 synchronous operation diagram ce2 = ce1# = h ce1# = h ce1# = l adv# low pulse & oe# = l adv# low pulse oe# = l oe# = h ce1# = h write suspend we# = l we# = h adv# low pulse write ce1# = l adv# low pulse & we# = l adv# low pulse (@bl = 8 or 16, and after burst o p eration is com p leted ) read standby read suspend ce1# = h ce1# = h
102 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 18 functional description this device supports asynchronous page read and normal write operation and synchronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as a user configurable option. 18.1 power up it is required to follow the power-up timing to start executing proper device operation. refer to power-up timing. after power-up, the device defaul ts to asynchronous page read & normal write operation mode with sleep power down feature. 18.2 configuration register the configuration register (cr) is used to config ure the type of device function among optional features. each selection of features is set throug h cr set sequence after power-up. if cr set se- quence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration. 18.3 cr set sequence the cr set requires total 6 read/write operations with unique address. between each read/write operation requires the device to be in stan dby mode. the following table shows the detail sequence. the first cycle is to read from most significant address (msb). the second and third cycle are to write to msb. if the second or third cycle is written into the different address, the cr set is cancelled and the data written by the second or third cycle is valid as a normal write operation. it is recommended to write back the data (rda) read by first cycle to msb in order to secure the data. the forth and fifth cycle is to write to msb. the da ta of forth and fifth cycle is don?t-care. if the forth or fifth cycle is written into different address, the cr set is also cancelled but write data may not be written as normal write operation. the last cycle is to read from specific address key for mode selection. and read data (rdb) is invalid. once this cr set sequence is performed from an initial cr set to the other new cr set, the written data stored in memory cell array may be lost. so, cr set sequence should be performed prior to regular read/write operation if necessary to change from default configuration. cycle # operation address data 1st read 3fffffh (msb) read data (rda) 2nd write 3fffffh rda 3rd write 3fffffh rda 4th write 3fffffh x 5th write 3fffffh x 6th read address key read data (rdb)
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 103 advance information 18.4 address key the address key has the following format. notes: 1. a21 and a6 to a0 must be all 1 in any case. 2. it is prohibited to apply this key. 3. if m=0, all the registers must be set wi th appropriate key input at the same time. 4. if m=1, ps must be set with appropriate key input at the same time. except for ps, all the other key inputs must be 1 . 5. burst read & single write is not supported at we# single clock pulse control. 6. effective only when ps=11. rp (reset to page) mode is available only for 64m. address pin register name function key description note 32m 64m a21 ? ? 1 ? unused bits muse be 1 1 a20-a19 ps partial size 00 8m partial 16m partial 01 4m partial 8m partial 10 reserved for future use 2 11 sleep [default] a18-a16 bl burst length 000 to 001 reserved for future use 2 010 8 words 011 16 words 100 to 110 reserved for future use 2 111 continuous a15 m mode 0 synchronous mode (burst read / write) 3 1 asynchronous mode [default] (page read / normal write) 4 a14-a12 rl read latency 000 reserved for future use 2 001 3 clocks 010 4 clocks 011 5 clocks 100 reserved for future use 6 clocks 101 to 111 reserved for future use 2 a11 bs burst sequence 0 reserved for future use 2 1 sequential a10 sw single write 0burst read & burst write 1 burst read & single write 5 a9 ve valid clock edge 0 falling clock edge 1 rising clock edge a8 rp reset to page 0 unused bits must be 1 reset to page mode 6 1 remain the previous mode a7 wc write control 0 we# single clock pulse control without write suspend function 5 1 we# level control with write suspend function a6-a0 ? ? 1 unused bits muse be 1 1
104 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 18.5 power down the power down is low power idle state controlled by ce2. ce2 low drives the device in power down mode and maintains low power idle state as long as ce2 is kept low. ce2 high resumes the device from power down mode. these devices ha ve three power down mode. these can be pro- grammed by series of read/write operat ions. each mode has following features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power- up. 64m supports reset to page (rp) mode. when rp=0, power down comprehends a function to reset the device to default configuration (asynchronous mode). after resuming from power down mode, the device is back in default configurations. this is effective only when ps is set on sleep mode. when partial mode is selected, rp=0 is not effective. 18.6 burst read/write operation synchronous burst read/write operation provides faster memory access that synchronized to mi- crocontroller or system bus frequency. configuration register set is required to perform burst read & write operation after power-up. once cr set sequence is performed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with cor- responding rl and bl that is se t through cr set sequence together with operation mode. in order to perform synchronous burst read & write operation, it is required to control new signals, clk, adv# and wait# that low power srams don?t have. 32m 64m mode data retention size retention address mode data retention size retention address sleep (default) no n/a sleep (default) no n/a 4m partial 4m bit 000000h to 03ffffh 8m partial 8m bit 000000h to 07ffffh 8m partial 8m bit 000000h to 07ffffh 16m partial 16m bit 000000h to 0fffffh figure 18.1 burst read operation a ddress adv# clk dq valid ce1# oe# wait# high-z high-z rl bl q 2 q bl q 1 we# high
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 105 advance information 18.7 clk input function the clk is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. the clk input increments device internal address counter and the valid edge of clk is referred for latency counts from address latch, burst write data latch, and burst read data out. during sy nchronous operation mode, clk input must be sup- plied except for standby state and power down st ate. clk is don?t care during asynchronous operation. 18.8 adv# input function the adv# is input signal to indicate valid address pr esence on address inputs. it is applicable to synchronous operation as well as asynchronous op eration. adv# input is active during ce1#=l and ce1#=h disables adv# input. all addresses are determined on the positive edge of adv#. during synchronous burst read/write operation, adv#=h disables all address inputs. once adv# is brought to high after valid address latch, it is inhibited to bring adv# low until the end of burst or until burst operation is terminated. adv# low pulse is mandatory for synchronous burst read/ write operation mode to latch the valid address input. during asynchronous operation, adv#=h also disa bles all address inputs. adv# can be tied to low during asynchronous operation and it is not necessary to control adv# to high. 18.9 wait# output function the wait# is output signal to indicate data bus status when the device is operating in synchro- nous burst mode. during burst read operation, wait# output is en abled after specified time duration from oe#=l or ce1#=l whichever occurs last. wait# output low indicates data out at next clock cycle is in- valid, and wait# output becomes high one clock cycle prior to valid data out. during oe# read suspend, wait# output doesn?t indicate data bus status but carries the same level from previous clock cycle (kept high) except for read suspend on the final data output. if final read data out is suspended, wait# output become high impedance after specified time duration from oe#=h. figure 18.2 burst write operation a ddress adv# clk dq valid ce1# oe# wait# high-z high-z rl-1 bl d 2 d bl d 1 we# high
106 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information in case of continuous burst read operation of 32m, an additional output delay may occur when a burst sequence crosses it?s device-row boundary. the wait# output indicates this delay. refer to the burst length for the additional delay cycles in details. during burst write operation, wait# output is enab led to high level after specified time duration from we#=l or ce1#=l whichever occurs last and kept high for entire write cycles including we# write suspend. the actual write data latching star ts on the appropriate clock edge with respect to valid clock edge, read latency and burst length. during we# write suspend, wait# output doesn?t indicate data bus status but carries the same level from previous clock cycle (kept high) except for write suspend on the final data input. if final write data in is suspended, wait# output become high impedance after specified time duration from we#=h. the burst write operation of 32m and the both burst read/write operation of 64m are always started after fixed latency with respect to read latency set in cr. when the device is operating in asynchronous mode, wait# output is always in high impedance. 18.10 latency read latency (rl) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burs t read operation. it is set through cr set se- quence after power-up. once specific rl is set through cr set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is auto- matically set to rl-1.the burst operation is always started after fixed latency with respect to read latency set in cr. rl=6 is available only for 64m.
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 107 advance information 18.11 address latch by adv# the adv# indicates valid address presence on address inputs. during synchronous burst read/ write operation mode, all the address are determ ined on the positive edge of adv# when ce1#=l. the specified minimum va lue of adv#=l setup time and hold time against valid edge of clock where rl count begin must be satisfied for appropriate rl counts. valid address must be determined with specified setup time against either the negative edge of adv# or negative edge of ce1# whichever comes late. and the determined valid address must not be changed during adv#=l period. figure 18.3 read latency diagram address adv# clk valid q1 q2 q3 d1 d2 d3 d4 0 12 345 rl=3 q4 d5 dq [out] dq [in] ce1# oe# or we# wait# wait# 6 q5 d5 q1 q2 d1 d2 d3 rl=4 q3 d4 dq [out] dq [in] wait# wait# q4 d5 q1 d1 d2 rl=5 q2 d3 dq [out] dq [in] wait# wait# q3 d4 high-z high-z high-z high-z high-z high-z d1 rl=6 q1 d2 dq [out] dq [in] wait# wait# q2 d3 high-z high-z
108 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 18.12 burst length burst length is the number of word to be read or write during synchronous burst read/write op- eration as the result of a single address latch cycle. it can be set on 8, 16 words boundary or continuous for entire address through cr set sequ ence. the burst type is sequential that is in- cremental decoding scheme within a boundary ad dress. starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (=0). after completing read data out or write data latch for the set burst le ngth, operation automatically ended except for con- tinuous burst length. when continuous burst length is set, read/write is endless unless it is terminated by the positive edge of ce1#. during continuous burst read of 32m, an addi tional output delay may occur when a burst se- quence cross it?s device-row boundary. this is the case when a0 to a6 of starting address is either 7dh, 7eh, or 7fh as shown in the following table. the wait# signal indicates this delay. the 64m device has no additional output delay. note: read address in hexadecimal. 18.13 single write single write is synchronous write operation with burst length =1. the device can be configured either to burst read & single write or to burst read & burst write through cr set sequence. once the device is configured to burst read & single write mode, the burst length for synchronous write operation is always fixed 1 regardless of bl values set in cr, while burst length for read is in accordance with bl values set in cr. 18.14 write control the device has two types of we# signal control method, we# level control and we# single clock pulse control , for synchronous write operation. it is configured through cr set sequence. start address (a6-a0) read address sequence bl = 8 bl = 16 continuous 00h 00-01-02-...-06-07 00-01-02 -...-0e-0f 00-01-02-03-04-... 01h 01-02-03-...-07-00 01-02-03-. ..-0f-00 01-02-03-04-05-... 02h 02-03-...-07-00-01 02-03-... -0f-00-01 02-03-04-05-06-... 03h 03-...-07-00-01-02 03-...-0f-00-01-02 03-04-05-06-07-... ... ... ... ... 7ch 7c-...-7f-78-...-7b 7c-...-7f- 70-...-7b 7c-7d-7e-7f-80-81-... 7dh 7d-7e-7f-78-...-7c 7d- 7e-7f-70-...-7c 7d-7e-7f- wait -80-81-... 7eh 7e-7f-78-79-...-7d 7e-7f-70-71-...-7d 7e-7f- wait - wait -80-81-... 7fh 7f-78-79-7a-...-7e 7f-70-71-72-...-7e 7f- wait - wait - wait -80-81
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 109 advance information 18.15 burst read suspend burst read operation can be suspended by oe# hi gh pulse. during burst read operation, oe# brought to high suspends burst read operation. once oe# is brought to high with the specified set up time against clock where the data being suspended, the device internal counter is sus- pended, and the data output become high impedance after specified time duration. it is inhibited to suspend the first data out at the beginning of burst read. oe# brought to low resumes burst read operation. once oe# is brought to low, data output be- come valid after specified time duration, and internal address counter is reactivated. the last data out being suspended as the result of oe#=h and first data out as the result of oe#=l are from the same address. in order to guarantee to output last data before suspension and first data after resumption, the specified minimum value of oe#=l hold time and se tup time against clock edge must be satisfied respectively. figure 18.4 write controls address adv# clk valid 0 12 345 ce1# we# 6 d1 d2 rl=5 d3 dq [in] wait# d4 we# d1 d2 d3 dq [in] wait# d4 high-z t wld high-z t wsck t ckwh t wlth t clth we# level control we# single clock pulse control t wlth
110 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 18.16 burst write suspend burst write operation can be suspended by we# high pulse. during burst write operation, we# brought to high suspends burst write operation. once we# is brought to high with the specified set up time against clock where the data being suspended, device internal counter is suspended, data input is ignored. it is inhibited to suspend the first data input at the beginning of burst write. we# brought to low resumes burst write operation. once we# is brought to low, data input be- come valid after specified time duration, and inte rnal address counter is reactivated. the write address of the cycle where data being suspended and the first write addr ess as the result of we#=l are the same address. in order to guarantee to latch the last data inpu t before suspension and first data input after re- sumption, the specified minimum value of we#=l hold time and setup time against clock edge must be satisfied respectively. burst write suspend function is available when the device is oper- ating in we# level controlled burst write only. figure 18.5 burst read suspend diagram figure 18.6 burst write suspend diagram q 2 dq oe# clk q 1 t ac t ckqx t olz t ac q 2 t ckqx t ac q 3 t ckqx t ac t ckoh t osck t ckoh t osck t ohz wait# t cktv q 4 dq we# d 1 t dhck t dsck t dsck d 2 t dhck t dsck t dsck d 3 t dhck t dsck t dsck t ckwh t wsck t ckwh t wsck d 2 d 4 wait# high clk
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 111 advance information 18.17 burst read termination burst read operation can be terminated by ce1# brought to high. if bl is set on continuous, burst read operation is continued endless unless terminated by ce1#=h. it is inhibited to terminate burst read before first data out is completed. in order to guarantee last data output, the specified minimum value of ce1#=l hold time from clock ed ge must be satisfied. after termination, the specified minimum recovery time is required to start new access. 18.18 burst write termination burst write operation can be terminated by ce1# brought to high. if bl is set on continuous, burst write operation is continued endless unless terminated by ce1#=h. it is inhibited to termi- nate burst write before first data in is complete d. in order to guarantee last write data being latched, the specified minimum values of ce1#=l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. figure 18.7 burst read termination diagram figure 18.8 burst write termination diagram a ddress adv# dq oe# clk valid ce1# wait# q 1 q 2 t ac t ckqx t ckclh t trb t ckoh t chz high-z t chtz t ohz a ddress adv# dq we# clk valid ce1# wait# t ckclh t trb t ckwh t chtz high-z d 2 d 1 t dhck t dhck t dsck t dsck t chck
112 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 19 absolute maximum ratings warning : semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 20 recommended operating conditions (see warning below) notes: 1. maximum dc voltage on input and i/o pins are v dd +0.2v. during voltage transitions, inputs may positive overshoot to v dd +1.0v for periods of up to 5 ns. 2. minimum dc voltage on input or i/o pins are -0.3v. during voltage transitions, inputs may negative overshoot v ss to -1.0v for periods of up to 5ns. warning : recommended operating conditions are normal operat ing ranges for the semiconductor device. all the de- vice?s electrical characteristics are warr anted when operated within these ranges. always use semiconductor devices within the recommended operating conditions . operation outside these ranges may adversely affect reliability and co uld result in device failure. no warranty is made with respect to uses, operating condit ions, or combinations not represented on the data sheet. 21 package pin capacitance test conditions: t a = 25c, f = 1.0 mhz item symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage at any pin relative to v ss v in , v out -0.5 to +3.6 v short circuit output current i out 50 ma storage temperature t stg -55 to +125 c parameter symbol 32m 64m unit min max min max supply voltage v dd 1.65 1.95 1.7 1.95 v v ss 00 0 0v high level input voltage (note 1) v ih v dd x 0.8 v dd +0.2 v dd x 0.8 v dd +0.2 v high level input voltage (note 2) v il -0.3 v dd x 0.2 -0.3 v dd x 0.2 v ambient temperature t a -30 85 -30 85 c symbol description test setup typ max unit c in1 address input capacitance v in = 0v ? 5 pf c in2 control input capacitance v in = 0v ? 5 pf c io data input/output capacitance v io = 0v ? 8 pf
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 113 advance information 22 dc characteristics (under recommended condition s unless otherwise noted) notes: 1. all voltages are referenced to v ss . 2. dc characteristics are measured after following power-up timing. 3. i out depends on the output load conditions. parameter symbol test conditions 32m 64m unit min. max. min. max. input leakage current i li v in = v ss to v dd -1.0 +1.0 -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ?0.5ma 2.4 ? 2.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 ? 0.4 v v dd power down current i ddps v dd = v dd max., v in = v ih or v il , ce2 0.2v sleep ? 10 ? tbd a i ddp4 4m partial ? 40 n/a a i ddp8 8m partial ? 50 ? tbd a i ddp16 16m partial n/a ? tbd v dd standby current i dds v dd = v dd max., v in (including clk)= v ih or v il , ce1# = ce2 = v ih ?1.5?tbdma i dds1 v dd = v dd max., v in (including clk) 0.2v or v in (including clk) v dd ? 0.2v, ce1# = ce2 v dd ? 0.2v ta +85c ? 80 ? tbd a ta +40c ? 80 ? tbd a v dd = v dd max., t ck =min. v in 0.2v or v in v dd ? 0.2v, ce1# = ce2 v dd ? 0.2v ? 200 ? tbd a v dd active current i dda1 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2= v ih , i out =0ma t rc / t wc = minimum ?30?35ma i dda2 t rc / t wc = 1 s ?3?5ma v dd page read current i dda3 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2= v ih , i out =0ma, t prc = min. ?10?tbdma v dd burst access current i dda4 v dd = v dd max., v in = v ih or v il , ce1# = v il and ce2= v ih , t ck = t ck min., bl = continuous, i out =0ma ?15?tbdma
114 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 23 ac characteristics (under recommended operating co nditions unless otherwise noted) 23.1 read operation notes: 1. maximum value is applicable if ce#1 is kept at low without change of address input of a3 to a21. 2. the output load 5pf without any other load. 3. applicable to a3 to a21 when ce1# is kept at low. 4. applicable only to a0, a1 and a2 when ce1# is kept at low for the page address access. 5. in case page read cycle is continued with keeping ce1# stay s low, ce1# must be brought to high within 4s. in other words, page read cycle must be closed within 4s. 6. t vpl is specified from the negative edge of either ce1# or adv# whichever comes late. the sum of t vpl and t vph must be equal or greater than trc for each access. 7. applicable to address access when at least two of address inputs are switched from previous state. 8. t rc (min) and t prc (min) must be satisfied. 9. if actual value of t whol is shorter than specified minimum values, the actual t aa of following read may become longer by the amount of subtracting actual value from specified minimum value. parameter symbol 32m 64m unit notes min. max. min. max. read cycle time t rc 70 1000 70 1000 ns ( 1 , 2 ) ce1# access time t ce ?70?70ns ( 3 ) oe# access time t oe ?40?40ns ( 3 ) address access time t aa ?70?70ns( 3 , 5 ) adv# access time t av 70 70 ns ( 3 ) lb# / ub# access time t ba ?30?30ns ( 3 ) page address access time t paa ?20?20ns( 3 , 6 ) page read cycle time t prc 20 1000 20 1000 ns ( 1 , 6 , 7 ) output data hold time t oh 5?5?ns( 3 ) ce1# low to output low-z t clz 5?5?ns( 4 ) oe# low to output low-z t olz 10 ? 0 ? ns ( 4 ) lb# / ub# low to output low-z t blz 0?0?ns( 4 ) ce1# high to output high-z t chz ?20?20ns ( 3 ) oe# high to output high-z t ohz ?20?20ns ( 3 ) lb# / ub# high to output high-z t bhz ?20?20ns ( 3 ) address setup time to ce1# low t asc ?5 ? ?5 ? ns address setup time to oe# low t aso 10 ? 10 ? ns adv# low pulse width t vpl 10 ? 10 ? ns ( 8 ) adv# high pulse width t vph 15 ? 15 ? ns ( 8 ) address setup time to adv high t asv 5?5?ns address hold time from adv# high t ahv 10 ? 5 ? ns address invalid time t ax ?10?10ns( 5 , 9 ) address hold time from ce1# high t chah ?5 ? ?5 ? ns address hold time from oe# high t ohah ?5 ? ?5 ? ns we# high to oe# low time for read t whol 15 1000 25 1000 ns ce1# high pulse width t cp 15 ? 15 ? ns
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 115 advance information 23.2 write operation notes: 1. maximum value is applicable if ce1# is kept at low without any address change. 2. minimum value must be equal or gr eater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wr ). 3. write pulse is defined from high to low transition of ce1#, we#, or lb# / ub#, whichever occurs last. 4. t vpl is specified from the negative edge of either ce#1 or adv# whichever comes late. the sum of t vpl and t vph must be equal or greater than t wc for each access. 5. applicable for byte mask only . byte mask setup time is defined to the high to low transition of ce1# or we# whichever occurs last. 6. applicable for byte mask only. byte mask hold time is defi ned from the low to high transition of ce1# or we# whichever occurs first. 7. write recovery is defined from low to high transiti on of ce1#, we#, or lb# / ub#, whichever occurs first. 8. if oe# is low after minimum t ohcl , read cycle is initiated. in other words, oe # must be brought to high within 5ns after ce1# is brought to low. once read cycle is initia ted, new write pulse should be input after minimum t rc is met. 9. if oe# is low after new address input, re ad cycle is initiated. in other word, oe# must be brought to high at the same time or before new address valid. once read cycle is in itiated, new write pulse shou ld be input after minimum t rc is met and data bus is in high-z. parameter symbol 32m 64m unit notes min. max. min. max. write cycle time t wc 70 1000 70 1000 ns ( 1 , 2 ) address setup time t as 0?0?ns( 3 ) adv# low pulse width t vpl 10 ? 10 ? ns ( 4 ) adv# high pulse width t vph 15 ? 15 ? ns address setup time to adv# high t asv 5?5?ns address hold time from adv# high t ahv 10 ? 5 ? ns ce1# write pulse width t cw 45 ? 45 ? ns ( 3 ) we# write pulse width t wp 45 ? 45 ? ns ( 3 ) lb# / ub# write pulse width t bw 45 ? 45 ? ns ( 3 ) lb# / ub# byte mask setup time t bs -5 ? ?5 ? ns ( 5 ) lb# / ub# byte mask hold time t bh -5 ? ?5 ? ns ( 6 ) ce1# write recovery time t wrc 15 ? 15 ? ns ( 7 ) write recovery time t wr 15 1000 15 1000 ns ( 7 ) ce1# high pulse width t cp 15 ? 15 ? ns we# high pulse width t whp 15 1000 15 1000 ns lb# / ub# high pulse width t bhp 15 1000 15 1000 ns data setup time t ds 15 ? 15 ? ns data hold time t dh 0?0?ns oe# high to ce1# low setup time for write t ohcl -5 ? ?5 ? ns ( 8 ) oe# high to address setup time for write t oes 0?0?ns( 9 ) lb# / ub# write pulse overlap t bwo 30 ? 30 ? ns
116 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 23.3 synchronous operation - clock input (burst mode) notes: 1. clock period is defined between valid clock edges. 2. clock rise/fall time is defined between v ih min. and v il max. 23.4 synchronous operation - address latch (burst mode) notes: 1. t ascl is applicable if ce1# is brought to low after adv# is brought to low. 2. t asvl is applicable if adv# is brought to low after ce1# is brought to low. 3. t vpl is specified from the negative edge of either ce1# or adv# whichever comes late. 4. applicable to the 1st valid clock edge. parameter symbol 32m 64m unit notes min. max. min. max. clock period rl = 6 t ck n/a 13 ? ns ( 1 ) rl = 5 15 ? 15 ? ns rl = 4 20 ? 18 ? ns rl = 3 30 ? 30 ns clock high time t ckh 5?4?ns clock low time t ckl 5?4?ns clock rise/fall time t ckt ?3?3ns( 2 ) parameter symbol 32m 64m unit notes min. max. min. max. address setup time to adv# low t asvl -5 ? -5 ? ns ( 1 ) address setup time to ce1# low t ascl -5 ? -5 ? ns ( 2 ) address hold time from adv# high t ahv 10 ? 5 ? ns adv# low pulse width t vpl 10 ? 10 ? ns ( 3 ) adv# low setup time to clk rl = 6, 5 t vsck 7 ?5?ns( 4 ) rl = 4, 3 ? 7 ? ns ( 4 ) ce1 low setup time to clk rl = 6, 5 t clck 7 ?5?ns( 4 ) rl = 4, 3 ? 7 ? ns ( 4 ) adv# low hold time from clk t ckvh 1?1?ns( 4 ) burst end adv# high hold time from clk t vhvl 15 ? 13 ? ns
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 117 advance information 23.5 synchronous read operation (burst mode) notes: 1. the output load 50pf with 50ohm termination to v dd *0.5 v. 2. wait# drives high at the beginning depending on oe# falling edge timing. 3. t cktv is guaranteed after t oltl (max) from oe# falling edge and t osck must be satisfied. 4. the output load is 5pf without any other load. 5. once they are determined, they must not be changed until the end of burst. 6. defined from the low to high transition of ce1# to the high to low transition of either adv# or ce1# whichever occurs late. parameter symbol 32m 64m unit notes min. max. min. max. burst read cycle time t rcb ? 8000 ? 4000 ns clk access time rl = 6, 5 t ac ?12 ?10ns 1 rl = 4, 3 ? 12 ns 1 output hold time from clk t ckqx 3?3?ns 1 ce1# low to wait# low t cltl 520520ns 1 oe# low to wait# low t oltl 0 20 0 20 ns 1, 2 adv# low to wait# low t vltl n/a 0 20 ns 1 clk to wait# valid time t cktv ? 12 ? 10 ns 1, 3 wait# valid hold time from clk t cktx 3?3?ns 1 ce1# low to output low-z t clz 5?5?ns 4 oe# low to output low-z t olz 10 ? 10 ? ns 4 lb#, ub# low to output low-z t blz 0?0?ns 4 ce1# high to output high-z t chz ?14?20ns 1 oe# high to output high-z t ohz ?14?20ns 1 lb#, ub# high to output high-z t bhz ?14?20ns 1 ce1# high to wait high-z t chtz ?20?20ns 1 oe# high to wait high-z t ohtz ?20?20ns 1 oe# low setup time to 1st data-out t olq 30 ? 30 ? ns ub#, lb# setup time to 1st data-out t blq 30 ? 26 ? ns 5 oe# setup time to clk t osck 5?5?ns oe# hold time from clk t ckoh 5?5?ns burst end ce1# low hold time from clk t ckclh 5?5?ns burst end ub#, lb# hold time from clk t ckbh 5?5?ns burst terminate recovery time bl=8, 16 t trb 30 ? 26 ? ns 6 bl=continuous 70 ? 70 ? ns 6
118 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 23.6 synchronous write operation (burst mode) notes: 1. defined from the valid input edge to the high to low transition of either adv#, ce1#, or we#, whichever occurs last. and once they are determined, they must not be changed until the end of burst. 2. the output load 50pf with 50ohm termination to v dd *0.5 v. 3. defined from the valid clock edge where last data-in being latc hed at the end of burst write to the high to low transition of either adv# or ce1# whichever occurs late for the next access. 4. defined from the low to high transition of ce1# to the high to low transition of either adv# or ce1# whichever occurs late fo r the next access. parameter symbol 32m 64m unit notes min. max. min. max. burst write cycle time t wcb ? 8000 ? 4000 ns data setup time to clock t dsck 7?5?ns data hold time from clk t dhck 3?3?ns we# low setup time to 1st data in t wld 30 ? 30 ? ns ub#, lb# setup time for write t bs -5 ? -5 ? ns 1 we# setup time to clk t wsck 5?5?ns we# hold time from clk t ckwh 5?5?ns ce1# low to wait# high t clth 520520ns 2 we# low to wait# high t wlth 020020ns 2 ce1# high to wait# high-z t chtz ?20?20ns 2 we# high to wait# high-z t whtz ?20?20ns 2 burst end ce1# low hold time from clk t ckclh 5?5?ns burst end ce1# high setup time to next clk t chck 5?5?ns burst end ub#, lb# hold time from clk t ckbh 5?5?ns burst write recovery time t wrb 30 26 ns burst terminate recovery time bl=8, 16 t trb 30 ? 26 ? ns 3 bl=continuous t trb 70 ? 70 ? ns 4
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 119 advance information 23.7 power down parameters notes: 1. applicable when rp=0 (reset to page mode). rp (reset to page ) mode is available only for 64m. 2. applicable also to power-up. 3. applicable when pa rtial mode is set. 23.8 other timing parameters notes: 1. some data might be written into any address location if t chwx (min) is not satisfied. 2. except for clock input transition time. 3. the input transition time (t t ) at ac testing is 5ns for asynchronous operation and 3ns for synchronous operation respectively. if actual t t is longer than 5ns or 3ns specified as ac test condition, it may violate ac specification of some timing parameters. see the ac test conditions 23.9 ac test conditions parameter symbol 32m 64m unit notes min. max. min. max. ce2 low setup time for power down entry t csp 20 ? 10 ? ns ce2 low hold time after power down entry t c2lp 70 ? 70 ? ns ce2 low hold time for reset to asynchronous mode t c2lpr n/a 50 ? s 1 ce1# high hold time foll owing ce2 high after power down exit [sleep mode only] t chh 300 ? 300 ? s 2 ce1# high hold time foll owing ce2 high after power down exit [not in sleep mode] t chhp 70 ? 70 ? s 3 ce1# high setup time following ce2 high after power down exit t chs 0?0?ns2 parameter symbol 32m 64m unit notes min. max. min. max. ce1 high to oe invalid time for standby entry t chox 10 ? 10 ? ns ce1 high to we invalid time for standby entry t chwx 10 ? 10 ? ns 1 ce2 low hold time after power-up t c2lh 50 ? 50 ? s ce1 high hold time following ce2 high after power-up t chh 300 ? 300 ? s input transition time t t 125125ns2 symbol description test setup value unit note v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time async. between v il and v ih 5ns sync. 3 ns
120 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information 23.10 ac measurement output load circuit figure 23.1 output load circuit device under test v dd v dd *0.5v v ss out 0.1 f 50pf 50ohm
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 121 advance information 24 timing diagrams note: this timing diagram assumes ce2=h and we#=h. note: this timing diagram assumes ce2=h and we#=h. figure 24.1 asynchronous read timing #1-1 (basic timing) figure 24.2 asynchronous read timing #1-2 (basic timing) t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz t oe t ba t blz adv# low lb# / ub# t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t cp t asc t asc t ohz t oh t bhz t oe t ba t blz adv# address valid t ahv t vpl t av lb# / ub#
122 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assume s ce2=h, adv#=l and we#=h. note: this timing diagram assume s ce2=h, adv#=l and we#=h. figure 24.3 asynchronous read timing #2 (oe# & address access) figure 24.4 asynchronous read timing #3 (lb# / ub# byte access) t aa valid data output address ce1# dq (output) t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso lb# / ub# t aa valid data output address dq1-8 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output ce1#, oe#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 123 advance information note: this timing diagram assumes ce2=h and we#=h. notes: 1. this timing diagram assumes ce2=h, adv#=l and we#=h. 2. either or both lb# and ub# must be low when both ce 1# and oe# are low. figure 24.5 asynchronous read timing #4 (p age address access after ce1# control access) figure 24.6 asynchronous read timing #5 (random and page address access) valid data output (normal access) address (a2-a0) ce1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa address (a21-a3) address valid t paa t oh t prc t paa t prc t oh address valid address valid t rc adv# t asc lb# / ub# valid data output (normal access) address (a2-a0) ce1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa address (a21-a3) address valid t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso lb# / ub#
124 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h and adv#=l. note: this timing diagram assumes ce2=h. figure 24.7 asynchronous write timing #1-1 (basic timing) figure 24.8 asynchronous write timing #1-2 (basic timing) t as valid data input address ce1# dq (input) we# t dh t ds t wc t wrc t wp t cw t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# low lb#, ub# t as valid data input a ddress ce1# dq (input) we# t dh t ds t wc t wrc t wp t cw t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# t vpl t ahv lb#, ub#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 125 advance information note: this timing diagram assumes ce2=h and adv#=l. note: this timing diagram assumes ce2=h, adv#=l and oe#=h. figure 24.9 asynchronous write timing #2 (we# control) figure 24.10 asynchronous write timing #3 -1 (we# / lb# / ub# byte write control) t as address we# ce1# t wc t wr t wp address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah ub#, lb# t as a ddress we# ce1# t wc t br t wp lb# address valid t as t br t wp valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh
126 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, adv#=l and oe#=h. note: this timing diagram assumes ce2=h, adv#=l and oe#=h. figure 24.11 asynchronous write timing #3-2 (we# / lb# / ub# byte write control) figure 24.12 asynchronous write timing #3-3 (we# / lb# / ub# byte write control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t as a ddress we# ce1# t wc t br t bw lb# address valid t as t br t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 127 advance information note: this timing diagram assumes ce2=h, adv#=l and oe#=h. notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. write address is valid from either ce1# or we# of last falling edge. figure 24.13 asynchronous write timing #3 -4 (we# / lb# / ub# byte write control) figure 24.14 asynchronous read / write timing #1-1 (ce1# control) t as a ddress we# ce1# t wc t br t bw lb# address valid t as t br t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo read data output address ce1# dq we# t wc t cw oe# t ohcl t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh ub#, lb#
128 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. oe# can be fixed low during write operation if it is ce1# controlled write at read-write-read sequence. notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 24.15 asynchronous read / write timing #1-2 (ce1# / we# / oe# control) figure 24.16 asynchronous read / write timing #2 (oe#, we# control) read data output address ce1# dq we# t wc t wp oe t ohcl t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output ub#, lb# read data output address ce1# dq we# t wc t wp oe# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah ub#, lb#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 129 advance information notes: 1. this timing diagram assumes ce2=h and adv#=l. 2. ce1# can be tied to low for we# and oe# controlled operation. notes: 1. stable clock input must be required during ce1#=l. 2. t ck is defined between valid clock edges. 3. t ckt is defined between v ih min. and v il max figure 24.17 asynchronous read / write timing #3 (oe,# we#, lb#, ub# control) figure 24.18 clock input timing read data output a ddress ce1# dq we# t wc t bw oe# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes ub#, lb# clk t ck t ckh t ckl t ckt t ckt t ck
130 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. case #1 is the timing when ce1# is brought to low after adv# is brought to low. case #2 is the timing when adv# is brought to low after ce1# is brought to low. 2. t vpl is specified from the negative edge of either ce1# or adv# wh ichever comes late. at least one va lid clock edge must be input d uring adv#=l. 3. t vsck and t clck are applied to the 1st valid clock edge during adv#=l. figure 24.19 address latch timing (synchronous mode) clk adv# a ddress ce 1# t ahv t vpl t asvl valid case #1 case #2 t vsck t ahv t vpl t vlcl valid t vsck t clck t ascl low t ckvh t ckvh
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 131 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.20 32m synchronous re ad timing #1 (oe# control) adv# dq we# oe# valid t asvl t ahv t vpl t clck t ascl wait# q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh t cktv valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t cktx t ckvh t ckvh ce1# lb#, ub# address clk
132 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.21 32m synchronous read timing #2 (ce1# control) addr e ss adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl t clck t ascl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cktv t cltl t ckbh t asvl t cktx t cktx t ckvh t ckvh
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 133 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.22 32m synchronous read timing #3 (adv# control) address adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx t cktv low low t cktx t cktx t ckvh t ckvh
134 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.23 synchronous read - wait# output timing (continuous read) xxx7fh t asvl t ahv t vpl t clck t ascl q 1 t olq t ac t ckqx t oltl t ac t cktv high high-z rl=5 t vsck t olz t cktv high-z q 2 t ckqx q 3 t ckqx t ac t ac t cktv t ac t blq t cktx t cktx t cktx t ckvh clk address adv# ce1# oe# we# lb#, ub# wait# dq
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 135 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.24 64m synchronous re ad timing #1 (oe# control) t ahv address adv# dq we# oe# clk valid ce1# t asvl t vpl t clck t ascl wait# q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t ckvh t ckvh lb#, ub#
136 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.25 64m synchronous read timing #2 (ce1# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cltl t ckbh t asvl t cktx t ckvh t ckvh lb#, ub#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 137 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.26 64m synchronous read timing #3 (adv# control) addr es s adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx low low t cktx t vltl t vltl t ckvh t ckvh
138 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.27 synchronous write timing #1 (we# level control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t ckvh t ckvh t asvl lb#, ub#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 139 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.28 synchronous write timing #2 (we# single clock pulse control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckclh valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t chtz t wlth t wsck t ckwh t ckwh t wsck t ckvh t ckvh lb#, ub#
140 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.29 synchronous write timing #3 (adv# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl wait# high rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb valid t asvl t ahv t vpl t vsck t bs t wrb t vsck t vhvl t ckbh high t ckvh t ckvh lb#, ub#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 141 advance information notes: 1. this timing diagram assumes ce2=h, the valid cloc k edge on rising edge and single write operation. 2. write data is latched on the valid clock edge. figure 24.30 synchronous write timing #4 (we# level control, single write) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 t dhck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t wlth t ckvh t ckvh t asvl lb#, ub#
142 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.31 32m synchronous read to write timing #1(ce1# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t clck t ascl wait# t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t cktv t vhvl t ckbh t ckbh t cktx t wcb t ckvh t clth lb#, ub#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 143 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.32 32m synchronous read to write timing #2(adv# control) address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl wait# t vsck t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t cktv t vhvl t ckbh t ckbh t cktx t ckvh t wlth lb#, ub#
144 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.33 64m synchronous read to write timing #1(ce1# control) addr ess adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl t clck t ascl wait# t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t vhvl t ckbh t ckbh t wcb t clth t ckvh
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 145 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.34 64m synchronous read to write timing #2(adv# control) addr es s adv# dq we# oe# lb#, ub# cl k valid ce 1# t asvl t ahv t vpl wait# t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t vhvl t ckbh t ckbh t wlth t ckvh t vsck
146 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.35 synchronous write to read timing #1 (ce1# control) d bl address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t ckt t clck t ascl wait# t vsck t cp rl=5 t ckclh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t cltl t clz t wrb t ckbh t cktx t ckvh t chtz high-z lb#, ub#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 147 advance information note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. figure 24.36 synchronous write to read timing #2 (adv# control) d bl address adv# dq we# oe# clk valid ce1# t asvl t ahv t vpl t ckt wait# low t vsck rl=5 t ckwh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t oltl t olz t olq t wrb t blq t ckbh t cktx t ckvh t whtz high-z lb#, ub#
148 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information note: the t c2lh specifies after v dd reaches specified minimum level. note: the t chh specifies after v dd reaches specified minimum level and applicable to both ce1# and ce2. note: this power down mode can be also used as a reset timi ng if the power-up timing above could not be satisfied and power-down program was not performed prior to this reset. figure 24.37 power-up timing #1 figure 24.38 power-up timing #2 figure 24.39 power down entry and exit timing t c2lh ce1# v dd v dd min 0v ce2 t chh t chs ce1# v dd v dd min 0v ce2 t chh t csp ce1# power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 149 advance information note: both t chox and t chwx define the earliest entry timing for standby mo de. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce1# low to high transition. notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in the cosmoram functional description . if not, the operation and data are not guaranteed. 3. after t cp or t rc following cycle #6, the configuration register set is completed and returned to the normal operation. t cp and t rc are applicable to returning to asynchronous mode and to synchronous mode respectively. 4. byte read or write is available in addition to word read or write. at least one byte control signal (lb# or ub#) need to be l ow. figure 24.40 standby entry timing after read or write figure 24.41 configuration register set timing #1 (asynchronous operation) t chox ce1# oe# we# active (read) standby active (write) standby t chwx address ce1# dq* 3 we# t rc oe# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb t cp * 3 (t rc ) lb#, ub#
150 s71ws512nx0/s71ws256nx0 based mcps s71ws-n-02_a2 april 11, 2005 advance information notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in the cosmoram functional description . if not, the operation and data are not guaranteed. 3. after t trb following cycle #6, the configuration register set is completed and returned to the normal operation. 4. byte read or write is available in addition to word read or write. at least one byte control signal (lb# or ub#) need to be l ow. figure 24.42 configuration register set timing #2 (synchronous operation) address adv# dq we# oe# clk ce1# wait# rda msb rda msb rda msb x msb x msb rdb key t rcb t wcb t wcb t wcb t wcb t rcb t trb t trb t trb t trb t trb cycle#1 cycle#2 cycle#3 cycle#4 cycle#5 cycle#6 t trb rl rl-1 rl-1 rl-1 rl-1 rl lb#, ub#
april 11, 2005 s71ws-n-02_a2 s71ws512nx0/s71ws256nx0 based mcps 151 advance information 25 revisions revision a (february 1, 2004) initial release revision a1 (february 9, 2005) updated document to include burst speed of 66 mhz updated publication number revision a2 (april 11, 2005) updated product selector guide and ordering information tables colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, deve loped and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuclear reaction control in nucle ar facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporatin g safety design measures into your facility and equipment such as re dundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty , express, implied, or stat utory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2004-2005 spansion llc. all righ ts reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion l lc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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